- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375268 > ADV471 (Analog Devices, Inc.) CMOS 80 MHz Monolithic Color Palette RAM-DACs(80MHz單片256×18彩色調(diào)色器RAM-D/A轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號(hào)： | ADV471 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 80 MHz Monolithic Color Palette RAM-DACs(80MHz單片256×18彩色調(diào)色器RAM-D/A轉(zhuǎn)換器) |
| 中文描述： | 80兆赫的CMOS單片調(diào)色板RAM的數(shù)模轉(zhuǎn)換器（80MHz的單片256 × 18彩色調(diào)色器RAM的的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 198K |
| 代理商： | ADV471 |
ADV478/ADV471
–7–
REV. B
CIRCUIT DE SCRIPT ION
MPU Interface
As illustrated in the functional block diagram, the ADV478 and
ADV471 support a standard MPU bus interface, allowing the
MPU direct access to the color palette RAM and overlay color
registers.
T he RS0–RS2 select inputs specify whether the MPU is access-
ing the address register, color palette RAM, overlay registers or
read mask register, as shown in T able I. T he 8-bit address reg-
ister is used to address the color palette RAM and overlay regis-
ters, eliminating the requirement for external address multiplexers.
T o write color data, the MPU writes to the address register (se-
lecting RAM or overlay write mode) with the address of the
color palette RAM location or overlay register to be modified.
T he MPU performs three successive write cycles (8 or 6 bits
each of red, green and blue), using RS0–RS2 to select either
the color palette RAM or overlay registers. During the blue
write cycle, the three bytes of color information are concat-
enated into a 24-bit word (18-bit word for the ADV471) and
written to the location specified by the address register. T he ad-
dress register then increments to the next location which the
MPU may modify by simply writing another sequence of red,
green and blue data.
T able I. Control Input T ruth T able
RS2
RS1
RS0
Addressed by MPU
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
l
0
Address Register (RAM Write Mode)
Address Register (RAM Read Mode)
Color Palette RAM
Pixel Read Mask Register
Address Register (Overlay Write Mode)
Address Register (Overlay Read Mode)
Overlay Registers
Reserved
T o read color data, the MPU loads the address register (select-
ing RAM or overlay read mode) with the address of the color
palette RAM location or overlay register to be read. T he MPU
performs three successive read cycles (8 or 6 bits each of red,
green and blue), using RS0–RS2 to select either the color pal-
ette RAM or overlay registers. Following the blue read cycle,
the address register increments to the next location which the
MPU may read by simply reading another sequence of red,
green and blue data.
When accessing the color palette RAM, the address register re-
sets to 00H following a blue read or write cycle to RAM loca-
tion FFH. When accessing the overlay color registers, the
address register increments following a blue read or write cycle.
However, while accessing the overlay color registers, the four
most significant bits of the address register (ADDR4-7) are ig-
nored.
T he MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM/overlay registers
and the color registers (R, G and B in the block diagram) are
synchronized by internal logic and occur in the period between
MPU accesses. As only one pixel clock cycle is required to
complete the transfer, the color palette RAM and overlay regis-
ters may be accessed at any time with no noticeable disturbance
on the display screen.
T o keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in T able II. T hey are reset to
zero when the MPU writes to the address register and are not
reset to zero when the MPU reads the address register. T he
MPU does not have access to these bits. T he other eight bits of
the address register, incremented following a blue read or write
cycle (ADDR0–7), are accessible to the MPU and are used to
address color palette RAM locations and overlay registers, as
shown in T able II. ADDR0 is the LSB when the MPU is ac-
cessing the RAM or overlay registers. T he MPU may read the
address register at any time without modifying its contents or
the existing read/write mode.
Figure 1 illustrates the MPU read/write timing.
T able II. Address Register (ADDR) Operation
Value
RS2
RS1
RS0
Addressed By MPU
ADDRa,b (Counts Modulo 3)
00
01
10
00H–FFH
X X X X 0000
X X X X 0001
X X X X 0010
Red Value
Green Value
Blue Value
Color Palette RAM
Reserved
Overlay Color 1
Overlay Color 2
Overlay Color 15
ADDR0–7 (Counts Binary)
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
X X X X 1111
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV473KP110 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-35 |
| ADV473KP135 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-35 |
| ADV473KP66 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-35 |
| ADV473KP80 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-55 |
| ADV473 | CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC(三通道,8位視頻RAM-DAC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV471KP35 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADV471KP35E | 制造商:Analog Devices 功能描述: |
| ADV471KP35-REEL | 制造商:Rochester Electronics LLC 功能描述:TRIPLE 6-BIT VIDEO DAC IC - Tape and Reel 制造商:Analog Devices 功能描述: |
| ADV471KP50 | 制造商:Rochester Electronics LLC 功能描述:TRIPLE 6 BIT VIDEO DAC IC - Bulk 制造商:Analog Devices 功能描述: |
| ADV471KP66 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。