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參數(shù)資料
| 型號： | ADV471 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS 80 MHz Monolithic Color Palette RAM-DACs(80MHz單片256×18彩色調(diào)色器RAM-D/A轉(zhuǎn)換器) |
| 中文描述： | 80兆赫的CMOS單片調(diào)色板RAM的數(shù)模轉(zhuǎn)換器（80MHz的單片256 × 18彩色調(diào)色器RAM的的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 198K |
| 代理商： | ADV471 |
ADV478/ADV471
–5–
REV. B
PIN FUNCT ION DE SCRIPT ION
Pin
Mnemonic
Function
BLANK
Composite blank control input (T T L compatible). A logic zero drives the analog outputs to the blanking level as
illustrated in T ables IV and V. It is latched on the rising edge of CLOCK . When
BLANK
is a logical zero, the
pixel and overlay inputs are ignored
Setup control input. Used to specify either a 0 IRE (SET UP = GND) or 7.5 IRE (SET UP = V
AA
) blanking
pedestal.
Composite sync control input (T T L compatible). A logical zero on this input switches off a 40 IRE current source
on the analog outputs (see Figures 3 and 4).
SYNC
does not override any other control or data input, as shown in
T ables IV and V; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge
of CLOCK .
Clock input (T T L compatible). T he rising edge of CLOCK latches the P0–P7, OL0–OL3,
SYNC
, and
BLANK
inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedi-
cated T T L buffer.
Pixel select inputs (T T L compatible). T hese inputs specify, on a pixel basis, which one of the 256 entries in the
color palette RAM is to be used to provide color information. T hey are latched on the rising edge of CLOCK . P0
is the LSB. Unused inputs should be connected to GND.
Overlay select inputs (T T L compatible). T hese inputs specify which palette is to be used to provide color informa-
tion, as illustrated in T able III. When accessing the overlay palette, the P0–P7 inputs are ignored. T hey are
latched on the rising edge of CLOCK . OL0 is the LSB. Unused inputs should be connected to GND.
Red, green, and blue current outputs. T hese high impedance current sources are capable of directly driving a
doubly terminated 75
coaxial cable (Figures 5 and 6).
Full-scale adjust control. Note that the IRE relationships in Figures 3 and 4 are maintained, regardless of the
full-scale output current.
When using an external voltage reference (Figure 5), a resistor (R
SET
) connected between this pin and GND
controls the magnitude of the full-scale video signal. T he relationship between R
SET
and the full-scale output
current on each output is:
R
SET
(
) =
K
×
1,000
×
V
REF
(
V
)/
I
OUT
(
mA
)
K
is defined in the table below, along with corresponding R
SET
values for doubly terminated 75
loads.
When using an external current reference (Figure 6), the relationship between I
REF
and the full-scale output
current on each output is:
I
REF
(
mA
) =
I
OUT
(
mA
)/
K
SET UP
SYNC
CLOCK
P0–P7
OL0–OL3
IOR, IOG, IOB
I
REF
Mode
Pedestal
K
R
SE T
(
V
)
6-Bit
8-Bit
6-Bit
8-Bit
7.5 IRE
7.5 IRE
0 IRE
0 IRE
3.170
3.195
3.000
3.025
147
147
147
147
COMP
Compensation pin. If an external voltage reference is used (Figure 5), this pin should be connected to OPA. If an
external current reference is used, this pin should be connected to I
REF
. A 0.1
μ
F ceramic capacitor must always be
used to bypass this pin to V
AA
.
Voltage reference input. If an external voltage reference is used (Figure 5), it must supply this input with a 1.2 V
(typical) reference. If an external current reference is used (Figure 6), this pin should be left floating, except for
the bypass capacitor. A 0.1
μ
F ceramic capacitor must always be used to decouple this input to V
AA
as shown in
Figures 5 and 6.
Reference amplifier output. If an external voltage reference is used (Figure 5), this pin must be connected to
COMP. When using an external current reference (Figure 6), this pin should be left floating.
Analog power. All V
AA
pins must be connected to the Analog Power Plane.
Analog ground. All GND pins must be connected to the Ground Plane.
Write control input (T T L compatible). D0–D7 data is latched on the rising edge of
WR
, and RS0–RS2 are
latched on the falling edge of
WR
during MPU write operations. See Figure 1.
V
REF
OPA
V
AA
GND
WR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV473KP110 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-35 |
| ADV473KP135 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-35 |
| ADV473KP66 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-35 |
| ADV473KP80 | Circular Connector; No. of Contacts:55; Series:LJTP02R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Box Mount Receptacle; Insert Arrangement:17-55 |
| ADV473 | CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC(三通道,8位視頻RAM-DAC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV471KP35 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADV471KP35E | 制造商:Analog Devices 功能描述: |
| ADV471KP35-REEL | 制造商:Rochester Electronics LLC 功能描述:TRIPLE 6-BIT VIDEO DAC IC - Tape and Reel 制造商:Analog Devices 功能描述: |
| ADV471KP50 | 制造商:Rochester Electronics LLC 功能描述:TRIPLE 6 BIT VIDEO DAC IC - Bulk 制造商:Analog Devices 功能描述: |
| ADV471KP66 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 80 MHz Monolithic 256 x 24(18) Color Palette RAM-DACs |
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