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參數(shù)資料
| 型號(hào)： | ADUC836BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DUAL 16BIT W/MCU 52-MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 7x16b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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ADuC836
–34–
ADuC836
–35–
programmed to appear at Pin 3 or Pin 12. It should be noted
that in 12-bit mode, the DAC voltage output will be updated
as soon as the DACL data SFR has been written; therefore, the
DAC data registers should be updated as DACH first, followed
by DACL.The 12-bit DAC data should be written into DACH/L
right-justified such that DACL contains the lower eight bits, and
the lower nibble of DACH contains the upper four bits.
Table XV. DACCON SFR Bit Designations
Bit
Name
Description
7
–––
Reserved for Future Use
6
–––
Reserved for Future Use
5
–––
Reserved for Future Use
4
DACPIN
DAC Output Pin Select.
Set by user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
3
DAC8
DAC 8-bit Mode Bit.
Set by user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs
of the DAC, and the 4 LSBs of the DAC are set to zero.
Cleared by user to operate the DAC in its normal 12-bit mode of operation.
2
DACRN
DAC Output Range Bit.
Set by user to configure DAC range of 0 to AVDD.
Cleared by user to configure DAC range of 0 V to 2.5 V (VREF).
1
DACCLR
DAC Clear Bit.
Set to 1 by user to enable normal DAC operation.
Cleared to 0 by user to reset DAC data registers DACL/H to zero.
0
DACEN
DAC Enable Bit.
Set to 1 by user to enable normal DAC operation.
Cleared to 0 by user to power down the DAC.
DACH/L
DAC Data Registers
Function
DAC Data Registers, written by user to update the DAC output.
SFR Address
DACL (DAC Data Low Byte)
FBH
DACH (DAC Data High Byte)
FCH
Power-On Default Value
00H
Both Registers
Bit Addressable
No
Both Registers
Using the D/A Converter
The on-chip D/A converter architecture consists of a resistor
string DAC followed by an output buffer amplifier, the functional
equivalent of which is illustrated in Figure 21.
R
ADuC836
AVDD
VREF
OUTPUT
BUFFER
DAC
12
HIGH-Z
DISABLE
(FROM MCU)
Figure 21. Resistor String DAC Functional Equivalent
Features of this architecture include inherent guaranteed monoto-
nicity and excellent differential linearity. As illustrated in Figure 21,
the reference source for the DAC is user selectable in software. It
can be either AVDD orVREF. In 0-to-AVDD mode, the DAC output
transfer function spans from 0 V to the voltage at the AVDD pin.
In 0-to-VREF mode, the DAC output transfer function spans from
0 V to the internal VREF (2.5V).The DAC output buffer amplifier
features a true rail-to-rail output stage implementation.This means
that, unloaded, each output is capable of swinging to within less than
100 mV of both AVDD and ground. Moreover, the DAC’s linear-
ity specification (when driving a 10 k resistive load to ground)
is guaranteed through the full transfer function except codes 0
to 48 in 0-to-VREF mode and 0 to 100 and 3950 to 4095 in 0-to-
VDD mode.
Linearity degradation near ground and VDD is caused by saturation
of the output amplifier, and a general representation of its effects
(neglecting offset and gain error) is illustrated in Figure 22.The
dotted line in Figure 22 indicates the ideal transfer function, and
the solid line represents what the transfer function might look
like with endpoint nonlinearities due to saturation of the output
amplifier.
DAC
The ADuC836 incorporates a 12-bit voltage output DAC
on-chip. It has a rail-to-rail voltage output buffer capable of driving
10 k/100 pF. It has two selectable ranges, 0 V to VREF (the inter-
nal band gap 2.5 V reference) and 0 V to AVDD. It can operate
in 12-bit or 8-bit mode.The DAC has a control register, DACCON,
and two data registers, DACH/L. The DAC output can be
REV. A
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