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| 型號(hào)： | ADUC836BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 58/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 7x16b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤(pán)，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC836
–60–
ADuC836
–61–
INTERRUPT SYSTEM
The ADuC836 provides a total of 11 interrupt sources with two priority levels.The control and configuration of the interrupt system
are carried out through three interrupt-related SFRs: the IE (Interrupt Enable) Register, IP (Interrupt Priority Register), and IEIP2
(Secondary Interrupt Enable/Priority SFR) Registers.Their bit definitions are given in the Tables XXXV to XXXVII.
IE
Interrupt Enable Register
SFR Address
A8H
Power-On Default Value
00H
Bit Addressable
Yes
Table XXXV. IE SFR Bit Designations
Bit
Name
Description
7
EA
Written by User to Enable 1 or Disable 0 All Interrupt Sources
6
EADC
Written by User to Enable 1 or Disable 0 ADC Interrupt
5
ET2
Written by User to Enable 1 or Disable 0 Timer 2 Interrupt
4
ES
Written by User to Enable 1 or Disable 0 UART Serial Port Interrupt
3
ET1
Written by User to Enable 1 or Disable 0 Timer 1 Interrupt
2
EX1
Written by User to Enable 1 or Disable 0 External Interrupt 1
1
ET0
Written by User to Enable 1 or Disable 0 Timer 0 Interrupt
0
EX0
Written by User to Enable 1 or Disable 0 External Interrupt 0
IP
Interrupt Priority Register
SFR Address
B8H
Power-On Default Value
00H
Bit Addressable
Yes
Table XXXVI. IP SFR Bit Designations
Bit
Name
Description
7
–––
Reserved for Future Use
6
PADC
Written by User to Select ADC Interrupt Priority (1 = High; 0 = Low)
5
PT2
Written by User to Select Timer 2 Interrupt Priority (1 = High; 0 = Low)
4
PS
Written by User to Select UART Serial Port Interrupt Priority (1 = High; 0 = Low)
3
PT1
Written by User to Select Timer 1 Interrupt Priority (1 = High; 0 = Low)
2
PX1
Written by User to Select External Interrupt 1 Priority (1 = High; 0 = Low)
1
PT0
Written by User to Select Timer 0 Interrupt Priority (1 = High; 0 = Low)
0
PX0
Written by User to Select External Interrupt 0 Priority (1 = High; 0 = Low)
IEIP2
Secondary Interrupt Enable and
Priority Register
SFR Address
A9H
Power-On Default Value
A0H
Bit Addressable
No
Table XXXVII. IEIP2 SFR Bit Designations
Bit
Name
Description
7
–––
Reserved for Future Use
6
PTI
Written by User to Select TIC Interrupt Priority (1 = High; 0 = Low)
5
PPSM
Written by User to Select Power Supply Monitor Interrupt Priority (1 = High; 0 = Low)
4
PSI
Written by User to Select SPI/I2C Serial Port Interrupt Priority (1 = High; 0 = Low)
3
–––
Reserved.This bit must be 0.
2
ETI
Written by User to Enable 1 or Disable 0 TIC Interrupt
1
EPSM
Written by User to Enable 1 or Disable 0 Power Supply Monitor Interrupt
0
ESI
Written by User to Enable 1 or Disable 0 SPI/I2C Serial Port Interrupt
REV. A
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