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參數(shù)資料
| 型號(hào)： | ADUC836BCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 62KB（62K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 7x16b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC836
–42–
ADuC836
–43–
Table XX. PSMCON SFR Bit Designations
Bit
Name
Description
7
CMPD
DVDD Comparator Bit.
This is a read-only bit and directly reflects the state of the DVDD comparator.
Read 1 indicates the DVDD supply is above its selected trip point.
Read 0 indicates the DVDD supply is below its selected trip point.
6
CMPA
AVDD Comparator Bit.
This is a read-only bit and directly reflects the state of the AVDD comparator.
Read 1 indicates the AVDD supply is above its selected trip point.
Read 0 indicates the AVDD supply is below its selected trip point.
5
PSMI
Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating low analog or digital
supply.The PSMI Bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain)
high, a 250 ms counter is started.When this counter times out, the PSMI interrupt is cleared. PSMI can also be
written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI.
4
TPD1
DVDD Trip Point Selection Bits.
3
TPD0
These bits select the DVDD trip point voltage as follows:
TPD1
TPD0
Selected DVDD Trip Point (V)
0
4.63
0
1
3.08
1
0
2.93
1
2.63
2
TPA1
AVDD Trip Point Selection Bits.
1
TPA0
These bits select the AVDD trip point voltage as follows:
TPA1
TPA0
Selected AVDD Trip Point (V)
0
4.63
0
1
3.08
1
0
2.93
1
2.63
0
PSMEN
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the Power Supply Monitor Circuit.
Cleared to 0 by the user to disable the Power Supply Monitor Circuit.
POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once enabled,
monitors both supplies (AVDD or DVDD) on the ADuC836. It will
indicate when any of the supply pins drops below one of four
user-selectable voltage trip points from 2.63 V to 4.63 V. For cor-
rect operation of the Power Supply Monitor function, AVDD must
be equal to or greater than 2.7 V. Monitor function is controlled via
the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor
will interrupt the core using the PSMI bit in the PSMCON SFR.
This bit will not be cleared until the failing power supply has
returned above the trip point for at least 250 ms.This monitor
function allows the user to save working registers to avoid possible
data loss due to the low supply condition, and also ensures that
normal code execution will not resume until a safe supply level
has been well established.The supply monitor is also protected
against spurious glitches triggering the interrupt circuit.
PSMCON
Power Supply Monitor Control Register
SFR Address
DFH
Power-On Default Value
DEH
Bit Addressable
No
REV. A
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