參數(shù)資料
型號: ADUC832
廠商: Analog Devices, Inc.
英文描述: MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU
中文描述: MicroConverter的,12位ADC和62 kBytes為嵌入式閃存MCU數(shù)模轉(zhuǎn)換器
文件頁數(shù): 45/80頁
文件大?。?/td> 1311K
代理商: ADUC832
REV. 0
ADuC832
–45–
WDCON
SFR Address
Power-On Default Value
Bit Addressable
Watchdog Timer Control Register
C0H
10H
Yes
Table XVI. WDCON SFR Bit Designations
Bit
Name
Description
7
6
5
4
PRE3
PRE2
PRE1
PRE0
Watchdog Timer Prescale Bits.
The Watchdog timeout period is given by the equation: t
WD
= (2
PRE
(2
9
/f
XTAL
))
(0
PRE
7; f
XTAL
= 32.768 kHz)
PRE3 PRE2 PRE1 PRE0
Timeout Period (ms) Action
0
0
0
0
15.6
0
0
0
1
31.2
0
0
1
0
62.5
0
0
1
1
125
0
1
0
0
250
0
1
0
1
500
0
1
1
0
1000
0
1
1
1
2000
1
0
0
0
0.0
PRE3
0 > 1000
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog will generate an interrupt response instead of a system
reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR
EA instruction and it is also a fixed, high priority interrupt. If the watchdog is not being used to
monitor the system, it can alternatively be used as a timer. The prescaler is used to set the timeout
period in which an interrupt will be generated.
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a
0
or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by user to enable the watchdog and clear its counters. If this bit is not set by the user
within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending
on WDIR.
Cleared under the following conditions: User writes
0,
Watchdog Reset
(WDIR =
0
); Hardware Reset; PSM Interrupt.
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit
must be set and the very next instruction must be a write instruction to the WDCON SFR.
For example:
CLR
EA
;disable interrupts while writing
;to WDT
SETB WDWR
;allow write to WDCON
MOV
WDCON, #72H ;enable WDT for 2.0s timeout
SETB EA
;enable interrupts again (if rqd)
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Immediate Reset
Reserved
3
WDIR
2
WDS
1
WDE
0
WDWR
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset or
interrupt within a reasonable amount of time if the ADuC832
enters an erroneous state, possibly due to a programming error or
electrical noise. The watchdog function can be disabled by clearing
the WDE (Watchdog Enable) bit in the Watchdog Control
(WDCON) SFR. When enabled, the watchdog circuit will gener-
ate a system reset or interrupt (WDS) if the user program fails
to set the watchdog (WDE) bit within a predetermined amount
of time (see PRE3
0 bits in WDCON). The watchdog timer itself
is a 16-bit counter that is clocked directly from the 32.768 kHz
external crystal. The watchdog time out interval can be adjusted
via the PRE3
0 bits in WDCON. Full control and status of the
watchdog timer function can be controlled via the watchdog timer
control SFR (WDCON). The WDCON SFR can only be written
by user software if the double write sequence described in WDWR
below is initiated on every write access to the WDCON SFR.
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