參數(shù)資料
型號: ADUC832
廠商: Analog Devices, Inc.
英文描述: MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU
中文描述: MicroConverter的,12位ADC和62 kBytes為嵌入式閃存MCU數(shù)模轉(zhuǎn)換器
文件頁數(shù): 35/80頁
文件大?。?/td> 1311K
代理商: ADUC832
REV. 0
ADuC832
–35–
ON-CHIP PLL
The ADuC832 is intended for use with a 32.768 kHz watch
crystal. A PLL locks onto a multiple (512) of this to provide a
stable 16.78 MHz clock for the system. The core can operate at
this frequency or at binary submultiples of it to allow power
saving in cases where maximum core performance is not
required. The default core clock is the PLL clock divided by
8 or
2.097152 MHz. The ADC clocks are also derived from the
Table X. PLLCON SFR Bit Designations
Bit
Name
Description
7
OSC_PD
Oscillator Power-Down Bit.
Set by user to halt the 32 kHz oscillator in power-down mode.
Cleared by user to enable the 32 kHz oscillator in power-down mode.
This feature allows the TIC to continue counting even in power-down mode.
PLL Lock Bit.
This is a read only bit.
Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock.
If the external crystal becomes subsequently disconnected, the PLL will rail and the core will halt.
Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystalclock. This
may be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL
output can be 16.78 MHz
±
20%.
Reserved for future use; should be written with “0.”
Reserved for future use; should be written with “0.”
Fast Interrupt Response Bit
Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency,
regardless of the configuration of the CD2–0 bits (see below). Once user code has returned from an
interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits.
Cleared by user to disable the fast interrupt response feature.
CPU (Core Clock) Divider Bits.
This number determines the frequency at which the microcontroller core will operate.
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
0
0
16.777216
0
0
1
8.388608
0
1
0
4.194304
0
1
1
2.097152
6
LOCK
5
4
3
----
----
FINT
2
1
0
CD2
CD1
CD0
(Default Core Clock
Frequency)
1
1
1
1
0
0
1
1
0
1
0
1
1.048576
0.524288
0.262144
0.131072
PLL clock, with the modulator rate being the same as the crys-
tal oscillator frequency. The above choice of frequencies ensures
that the modulators and the core will be synchronous, regardless
of the core clock rate. The PLL control register is PLLCON.
PLLCON
SFR Address
Power-On Default Value
Bit Addressable
PLL Control Register
D7H
53H
No
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