參數(shù)資料
型號(hào)： ADUC832
廠商： Analog Devices, Inc.
英文描述： MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU
中文描述： MicroConverter的，12位ADC和62 kBytes為嵌入式閃存MCU數(shù)模轉(zhuǎn)換器
文件頁數(shù)： 20/80頁
文件大?。?/td> 1311K
代理商： ADUC832
REV. 0
–20–
ADuC832
Table IV. ADCCON2 SFR Bit Designations
Bit
Name
Description
ADCCON2.7 ADCI
The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at
the end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC
Interrupt Service Routine. Otherwise, the ADCI bit should be cleared by user code.
The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode opera-
tion. A more detailed description of this mode is given in the ADC DMA Mode section. The DMA bit is
automatically set to
“
0
”
at the end of a DMA cycle. Setting this bit causes the ALE output to cease, it will
start again when DMA is started and will operate correctly after DMA is complete.
The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of
conversion. In this mode, the ADC starts converting based on the timing and channel configuration
already set up in the ADCCON SFRs; the ADC automatically starts another conversion once a previ-
ous conversion has completed.
The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is
automatically reset to
“
0
”
on completion of the single conversion cycle.
The channel selection bits (CS3
–
0) allow the user to program the ADC channel selection under
software control. When a conversion is initiated, the channel converted will be that pointed to by
these channel selection bits. In DMA mode, the channel selection is derived from the channel ID
written to the external memory.
CS3 CS2 CS1 CS0 CH#
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
Temp Monitor
Requires minimum of 1
μ
s to acquire
1
0
0
1
DAC0
Only use with Internal DAC o/p buffer on
1
0
1
0
DAC1
Only use with Internal DAC o/p buffer on
1
0
1
1
AGND
1
1
0
0
VREF
1
1
1
1
DMA STOP
Place in XRAM location to finish DMA sequence, see
the section ADC DMA Mode.
All other combinations reserved
ADCCON2.6 DMA
ADCCON2.5 CCONV
ADCCON2.4 SCONV
ADCCON2.3 CS3
ADCCON2.2 CS2
ADCCON2.1 CS1
ADCCON2.0 CS0
ADCCON2 – (ADC Control SFR #2)
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
D8H
00H
YES
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