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參數(shù)資料
| 型號： | ADUC832 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU |
| 中文描述： | MicroConverter的，12位ADC和62 kBytes為嵌入式閃存MCU數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 39/80頁 |
| 文件大?。?/td> | 1311K |
| 代理商： | ADUC832 |
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REV. 0
ADuC832
–39–
SERIAL PERIPHERAL INTERFACE
The ADuC832 integrates a complete hardware Serial Peripheral
Interface (SPI) on-chip. SPI is an industry standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, i.e., full duplex. It should
be noted that the SPI pins are shared with the I
2
C pins. Therefore,
the user can only enable one or the other interface at any given
time (see SPE in Table XII). The SPI port can be configured for
Master or Slave operation and typically consists of four pins, namely:
MISO (Master In, Slave Out Data I/O Pin)
The MISO (master in slave out) pin is configured as an input line
in master mode and an output line in slave mode. The MISO line
on the master (data in) should be connected to the MISO line
in the slave device (data out). The data is transferred as byte
wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (master out slave in) pin is configured as an output
line in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLOCK (Serial Clock I/O Pin)
The master serial clock (SCLOCK) is used to synchronize the
data being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in each
SCLOCK period. Therefore, a byte is transmitted/received after
eight SCLOCK periods. The SCLOCK pin is configured as an
output in master mode and as an input in slave mode. In master
mode the bit-rate, polarity, and phase of the clock are controlled
by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XII). In slave mode the SPICON register will have to
be configured with the phase and polarity (CPHA and CPOL) of
the expected input clock. In both master and slave modes the
data is transmitted on one edge of the SCLOCK signal and sampled
on the other. It is important therefore that the CPHA and CPOL
are configured the same for the master and slave devices.
SS
(Slave Select Input Pin)
The Slave Select (
SS
) input pin is shared with the ADC5 input.
In order to configure this pin as a digital input, the bit must be
cleared, e.g., CLR P1.5.
This line is active low. Data is only received or transmitted in
slave mode when the
SS
pin is low, allowing the ADuC832 to be
used in single master, multislave SPI configurations. If CPHA = 1
then the
SS
input may be permanently pulled low. With CPHA = 0,
the
SS
input must be driven low before the first bit in a byte
wide transmission or reception and return high again after the
last bit in that byte wide transmission or reception. In SPI slave
mode, the logic level on the external
SS
pin can be read via the
SPR0 bit in the SPICON SFR.
The following SFR registers are used to control the SPI interface.
SPICON
SFR Address
Power-On Default Value
Bit Addressable
SPI Control Register
F8H
O4H
Yes
Table XII. SPICON SFR Bit Designations
Bit
Name
Description
7
ISPI
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable the I
2
C pins.
SPI Master/Slave Mode Select Bit.
Set by user to enable Master Mode operation (SCLOCK is an output).
Cleared by user to enable Slave Mode operation (SCLOCK is an input).
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
SPI Bit-Rate Select Bits.
These bits select the SCLOCK rate (bitrate) in master mode as follows:
SPR1
SPR0
Selected Bit Rate
0
0
f
OSC
/2
0
1
f
OSC
/4
1
0
f
OSC
/8
1
1
f
OSC
/16
In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external
SS
pin can be read via the SPR0 bit.
6
WCOL
5
SPE
4
SPIM
3
CPOL
2
CPHA
1
0
SPR1
SPR0
The CPOL and CPHA bits should both contain the same values for master and slave devices.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC832BCP | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 3V/5V 56-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 16.78MHZ 3.3/5V 56LFCSP - Bulk |
| ADUC832BCP-REEL | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 3V/5V 56-Pin LFCSP EP T/R |
| ADUC832BCPZ | 功能描述:IC MCU 62K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設(shè)備:欠壓檢測/復(fù)位，POR，WDT 輸入/輸出數(shù):40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
| ADUC832BCPZ-REEL | 功能描述:IC MCU 62K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC832BS | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 16.78MHZ 3.3/5V 52MQFP - Bulk 制造商:Analog Devices 功能描述:8BIT MCU +12BIT ADC LQFP52 832 |
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