參數(shù)資料
型號： ADUC7128BSTZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 87/92頁
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
Process Control
Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 28
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LQFP
包裝： 標(biāo)準(zhǔn)包裝
配用： EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128
其它名稱： ADUC7128BSTZ126-RLDKR
ADuC7128/ADuC7129
Rev. 0 | Page 88 of 92
In these cases, tie the AGND pins and IOGND pins of the
ADuC7128/ADuC7129 to the analog ground plane, as shown
in Figure 69b. In systems with only one ground plane, ensure
that the digital and analog components are physically separated
onto separate halves of the board such that digital return currents
do not flow near analog circuitry and vice versa. The ADuC7128/
ADuC7129 can then be placed between the digital and analog
sections, as illustrated in Figure 69c.
a.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
b.
PLACE ANALOG
COMPONENTS
HERE
PLACE DIGITAL
COMPONENTS HERE
AGND
DGND
c.
PLACE ANALOG
COMPONENTS HERE
PLACE DIGITAL
COMPONENTS HERE
GND
06
02
0-
0
59
Figure 69. System Grounding Schemes
In all of these scenarios, and in more complicated real-life
applications, keep in mind the flow of current from the supplies
and back to ground. Make sure the return paths for all currents
are as close as possible to the paths the currents took to reach
their destinations. For example, do not power components on
the analog side (see Figure 69b) with IOVDD since that would
force return currents from IOVDD to flow through AGND.
Avoid digital currents from flowing under analog circuitry,
which could happen if the user places a noisy digital chip on the
left half of the board (see Figure 69c). Whenever possible, avoid
large discontinuities in the ground planes (such as are formed
by a long trace on the same layer) because they force return
signals to travel a longer path. Make all connections to the ground
plane directly, with little or no trace separating the pin from its
via to ground.
If a user plans to connect fast logic signals (rise/fall time < 5 ns)
to any of the digital inputs of the ADuC7128/ADuC7129, add
a series resistor to each relevant line to keep rise and fall times
longer than 5 ns at the ADuC7128/ADuC7129 input pins.
A value of 100 Ω or 200 Ω is usually sufficient to prevent high
speed signals from coupling capacitively into the ADuC7128/
ADuC7129 and affecting the accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7128/ADuC7129 can be gener-
ated by the internal PLL or by an external clock input. To use
the internal PLL, connect a 32.768 kHz parallel resonant crystal
between XCLKI and XCLKO as shown Figure 70. External
capacitors should be connected as per the crystal manufacturer’s
recommendations. Note that the crystal pads already have an
internal capacitance of typically 10 pF. Users should ensure that
the total capacitance (10 pF internal + external capacitance)
does not exceed the manufacturer rating.
The 32 kHz crystal allows the PLL to lock correctly to give a
frequency of 41.78 MHz. If no external crystal is present, the
internal oscillator is used to give a frequency of 41.78 MHz ±
3% typically.
ADuC7128
TO
INTERNAL
PLL
12pF
XCLKI
32.768kHz
12pF
XCLKO
06
02
0-
06
0
Figure 70. External Parallel Resonant Crystal Connections
To use an external source clock input instead of the PLL, Bit 1
and Bit 0 of PLLCON must be modified. The external clock
uses the XCLK pin.
ADuC7128
TO
FREQUENCY
DIVIDER
XCLKI
XCLK
EXTERNAL
CLOCK
SOURCE
06
02
0
-06
1
Figure 71. Connecting an External Clock Source
Whether using the internal PLL or an external clock source, the
specified operational clock speed range of the ADuC7128/
ADuC7129 is 50 kHz to 41.78 MHz to ensure correct operation
of the analog peripherals and Flash/EE.
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