參數(shù)資料
型號(hào)： ADUC7128BSTZ126-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 79/92頁(yè)
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
Process Control
Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 28
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LQFP
包裝： 標(biāo)準(zhǔn)包裝
配用： EVAL-ADUC7128QSPZ-ND - KIT DEV FOR ADUC7128
其它名稱： ADUC7128BSTZ126-RLDKR
ADuC7128/ADuC7129
Rev. 0 | Page 80 of 92
Table 115. T3CON MMR Bit Designations
Bit
Value
Description
16:9
These bits are reserved and should be written as 0s by user code.
8
Count Up/Down Enable.
Set by user code to configure Timer3 to count up.
Cleared by user code to configure Timer3 to count down.
7
Timer3 Enable.
Set by user code to enable Timer3.
Cleared by user code to disable Timer3.
6
Timer3 Operating Mode.
Set by user code to configure Timer3 to operate in periodic mode.
Cleared by user to configure Timer3 to operate in free-running mode.
5
Watchdog Timer Mode Enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
4
Secure Clear Bit.
Set by user to use the secure clear option.
Cleared by user to disable the secure clear option by default.
3:2
Timer3 Clock (32.768 kHz) Prescaler.
00
Source Clock/1 (Default).
01
Reserved.
10
Reserved.
11
Reserved.
1
Watchdog Timer IRQ Enable.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
0
PD_OFF.
Set by user code to stop Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.
Cleared by user code to enable Timer3 when the peripherals are powered down via Bit 4 in the POWCON MMR.
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3ICLR
to avoid a watchdog reset. The value is a sequence generated by
the 8-bit linear feedback shift register (LFSR) polynomial equal
to X8 + X6 + X5 + X + 1, as shown in Figure 59.
CLOCK
QD
4
QD
5
QD
3
QD
7
QD
6
QD
2
QD
1
QD
0
06020-
054
Figure 59. 8-Bit LFSR
The initial value or seed is written to T3ICLR before entering
watchdog mode. After entering watchdog mode, a write to
T3ICLR must match this expected value. If it matches, the LFSR
is advanced to the next state when the counter reload happens.
If it fails to match the expected state, reset is immediately
generated, even if the count has not yet expired.
The value 0x00 should not be used as an initial seed due to the
properties of the polynomial. The value 0x00 is always guaran-
teed to force an immediate reset. The value of the LFSR cannot
be read; it must be tracked/generated in software.
The following is an example of a sequence:
1.
Enter initial seed, 0 xAA, in T3ICLR before starting
Timer3 in watchdog mode.
2.
Enter 0 xAA in T3ICLR; Timer3 is reloaded.
3.
Enter 0x37 in T3ICLR; Timer3 is reloaded.
4.
Enter 0x6E in T3ICLR; Timer3 is reloaded.
5.
Enter 0x66. 0xDC was expected; the watchdog resets
the chip.
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