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參數資料
| 型號： | ADUC7024BSTZ62-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 98/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 64-LQFP |
| 設計資源： | Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133) |
| 標準包裝： | 1,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數： | 30 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數據轉換器： | A/D 10x12b; D/A 2x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 帶卷 (TR) |
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Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 93 of 104
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7019/20/21/22/24/25/26/27/28/29 operational power
supply voltage range is 2.7 V to 3.6 V. Separate analog and
digital power supply pins (AVDD and IOVDD, respectively) allow
AVDD to be kept relatively free of noisy digital signals often
present on the system IOVDD line. In this mode, the part can
also operate with split supplies; that is, it can use different
voltage levels for each supply. For example, the system can
be designed to operate with an IOVDD voltage level of 3.3 V
whereas the AVDD level can be at 3 V or vice versa. A typical
split supply configuration is shown in Figure 87.
04955-
044
ADuC7026
0.1F
ANALOG
SUPPLY
10F
73
74
AVDD
75
DACVDD
8
GNDREF
70
DACGND
71
AGND
67
REFGND
26
IOVDD
54
25
IOGND
53
0.1F
+
–
DIGITAL
SUPPLY
10F
+
–
Figure 87. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and IOVDD and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 88. With this configuration, other analog circuitry
(such as op amps and voltage reference) can be powered from
the AVDD supply line as well.
04955-
045
ADuC7026
0.1F
BEAD
1.6
73
74
AVDD
75
DACVDD
8
GNDREF
70
DACGND
71
AGND
67
REFGND
26
IOVDD
54
25
IOGND
53
0.1F
DIGITAL SUPPLY
10F
+
–
Figure 88. External Single Supply Connections
Note that in both Figure 87 and Figure 88, a large value (10 F)
reservoir capacitor sits on IOVDD, and a separate 10 F capacitor
sits on AVDD. In addition, local small-value (0.1 F) capacitors are
located at each AVDD and IOVDD pin of the chip. As per standard
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AVDD pin with trace
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
Finally, note that the analog and digital ground pins on the
ADuC7019/20/21/22/24/25/26/27/28/29 must be referenced to
the same system ground reference point at all times.
IOVDD Supply Sensitivity
The IOVDD supply is sensitive to high frequency noise because it
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
is recommended.
ADuC7026
26
IOVDD
54
25
IOGND
53
0.1F
DIGITAL
SUPPLY
10F
+
–
1H
04955-
087
Figure 89. Recommended IOVDD Supply Filter
Linear Voltage Regulator
Each ADuC7019/20/21/22/24/25/26/27/28/29 requires a single
3.3 V supply, but the core logic requires a 2.6 V supply. An on-
chip linear regulator generates the 2.6 V from IOVDD for the
core logic. The LVDD pin is the 2.6 V supply for the core logic.
An external compensation capacitor of 0.47 F must be
connected between LVDD and DGND (as close as possible to
these pins) to act as a tank of charge as shown in Figure 90.
04955-
046
ADuC7026
0.47
mF
27 LVDD
28 DGND
Figure 90. Voltage Regulator Connections
The LVDD pin should not be used for any other chip. It is also
recommended to use excellent power supply decoupling on
IOVDD to help improve line regulation performance of the on-
chip voltage regulator.
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