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參數(shù)資料
| 型號： | ADUC7024BSTZ62-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 84/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 1MSPS UART 64-LQFP |
| 設(shè)計(jì)資源： | Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 30 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 帶卷 (TR) |
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ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 80 of 104
PROGRAMMABLE LOGIC ARRAY (PLA)
Every ADuC7019/20/21/22/24/25/26/27/28/29 integrates a
fully programmable logic array (PLA) that consists of two
independent but interconnected PLA blocks. Each block
consists of eight PLA elements, giving each part a total of
16 PLA elements.
Each PLA element contains a two-input lookup table that can
be configured to generate any logic output function based on
two inputs and a flip-flop. This is represented in Figure 76.
04
95
5-
0
33
4
2
0
1
3
A
B
LOOKUP
TABLE
Figure 76. PLA Element
In total, 30 GPIO pins are available on each ADuC7019/20/21/
22/24/25/26/27/28/29 for the PLA. These include 16 input pins
and 14 output pins, which msut be configured in the GPxCON
register as PLA pins before using the PLA. Note that the
comparator output is also included as one of the 16 input pins.
The PLA is configured via a set of user MMRs. The output(s) of
the PLA can be routed to the internal interrupt system, to the
CONVSTART signal of the ADC, to an MMR, or to any of the 16
PLA output pins.
The two blocks can be interconnected as follows:
Output of Element 15 (Block 1) can be fed back to Input 0
of Mux 0 of Element 0 (Block 0).
Output of Element 7 (Block 0) can be fed back to the Input 0
of Mux 0 of Element 8 (Block 1).
Table 145. Element Input/Output
PLA Block 0
PLA Block 1
Element
Input
Output
Element
Input
Output
0
P1.0
P1.7
8
P3.0
P4.0
1
P1.1
P0.4
9
P3.1
P4.1
2
P1.2
P0.5
10
P3.2
P4.2
3
P1.3
P0.6
11
P3.3
P4.3
4
P1.4
P0.7
12
P3.4
P4.4
5
P1.5
P2.0
13
P3.5
P4.5
6
P1.6
P2.1
14
P3.6
P4.6
7
P0.0
P2.2
15
P3.7
P4.7
PLA MMRs Interface
The PLA peripheral interface consists of the 22 MMRs
described in this section.
Table 146. PLAELMx Registers
Name
Address
Default Value
Access
PLAELM0
0xFFFF0B00
0x0000
R/W
PLAELM1
0xFFFF0B04
0x0000
R/W
PLAELM2
0xFFFF0B08
0x0000
R/W
PLAELM3
0xFFFF0B0C
0x0000
R/W
PLAELM4
0xFFFF0B10
0x0000
R/W
PLAELM5
0xFFFF0B14
0x0000
R/W
PLAELM6
0xFFFF0B18
0x0000
R/W
PLAELM7
0xFFFF0B1C
0x0000
R/W
PLAELM8
0xFFFF0B20
0x0000
R/W
PLAELM9
0xFFFF0B24
0x0000
R/W
PLAELM10
0xFFFF0B28
0x0000
R/W
PLAELM11
0xFFFF0B2C
0x0000
R/W
PLAELM12
0xFFFF0B30
0x0000
R/W
PLAELM13
0xFFFF0B34
0x0000
R/W
PLAELM14
0xFFFF0B38
0x0000
R/W
PLAELM15
0xFFFF0B3C
0x0000
R/W
PLAELMx are Element 0 to Element 15 control registers. They
configure the input and output mux of each element, select the
function in the lookup table, and bypass/use the flip-flop. See
Table 147. PLAELMx MMR Bit Descriptions
Bit
Value
Description
31:11
Reserved.
10:9
Mux 0 control (see Table 152).
8:7
Mux 1 control (see Table 152).
6
Mux 2 control. Set by user to select the output
of Mux 0. Cleared by user to select the bit value
from PLADIN.
5
Mux 3 control. Set by user to select the input
pin of the particular element. Cleared by user to
select the output of Mux 1.
4:1
Lookup table control.
0000
0.
0001
NOR.
0010
B AND NOT A.
0011
NOT A.
0100
A AND NOT B.
0101
NOT B.
0110
EXOR.
0111
NAND.
1000
AND.
1001
EXNOR.
1010
B.
1011
NOT A OR B.
1100
A.
1101
A OR NOT B.
1110
OR.
1111
1.
0
Mux 4 control. Set by user to bypass the flip-
flop. Cleared by user to select the flip-flop
(cleared by default).
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