參數(shù)資料
型號: ADUC7024BSTZ62-RL
廠商: Analog Devices Inc
文件頁數(shù): 71/104頁
文件大?。?/td> 0K
描述: IC MCU 12BIT 1MSPS UART 64-LQFP
設(shè)計(jì)資源: Sensing Low-g Acceleration Using ADXL345 Digital Accelerometer Connected to ADuC7024 (CN0133)
標(biāo)準(zhǔn)包裝: 1,500
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 44MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: PLA,PWM,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 2K x 32
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LQFP
包裝: 帶卷 (TR)
Data Sheet
ADuC7019/20/21/22/24/25/26/27/28/29
Rev. F | Page 69 of 104
Table 83. GPIO Drive Strength Control Bits Descriptions
Control Bits Value
Description
00
Medium drive strength.
01
Low drive strength.
1x
High drive strength.
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
–24
–18
–12
–6
0
6
12
18
24
LOAD CURRENT (mA)
V
O
L
T
AG
E
O
N
E
ACH
P
IN
(
V
)
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
04955-
031
Figure 73. Programmable Strength for High Level
(Typical Values)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–24
–18
–12
–6
0
6
12
18
24
LOAD CURRENT (mA)
V
O
L
T
AG
E
O
N
E
ACH
P
IN
(
V
)
HIGH DRIVE STRENGTH
MEDIUM DRIVE STRENGTH
LOW DRIVE STRENGTH
04955-
032
Figure 74. Programmable Strength for Low Level
(Typical Values)
The drive strength bits can be written to one time only after
reset. More writing to related bits has no effect on changing
drive strength. The GPIO drive strength and pull-up disable is
not always adjustable for the GPIO port. Some control bits
cannot be changed (see Table 84).
Table 84. GPxPAR Control Bits Access Descriptions
Bit
GP0PAR
GP1PAR
31
Reserved
30 to 29
R/W
28
R/W
27
Reserved
26 to 25
R/W
24
R/W
23
Reserved
22 to 21
R/W
R (b00)
20
R/W
19
Reserved
18 to 17
R (b00)
16
R/W
15
Reserved
14 to 13
R (b00)
12
R/W
11
Reserved
10 to 9
R (b00)
8
R/W
7
Reserved
6 to 5
R (b00)
4
R/W
3
Reserved
2 to 1
R (b00)
0
R/W
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