參數(shù)資料
型號(hào): ADUC7023BCP6Z62IRL
廠商: Analog Devices Inc
文件頁數(shù): 69/96頁
文件大小: 0K
描述: IC MCU 12BIT 62KB FLASH 40LFCSP
標(biāo)準(zhǔn)包裝: 2,500
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 44MHz
連通性: I²C,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2K x 32
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12 x12b; D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
Data Sheet
ADuC7023
| Page 71 of 96
PULSE-WIDTH MODULATOR
PULSE-WIDTH MODULATOR GENERAL OVERVIEW
The ADuC7023 integrates a 5-channel pulse-width modulator
(PWM) interface. The PWM outputs can be configured to drive
an H-bridge or can be used as standard PWM outputs. On
power-up, the PWM outputs default to H-bridge mode. This
ensures that the motor is turned off by default. In standard
PWM mode, the outputs are arranged as three pairs of PWM
pins. Users have control over the period of each pair of outputs
and over the duty cycle of each individual output.
Table 84. PWM MMRs
MMR Name
Description
PWMCON1
PWM Control Register 1.
PWM0COM0
Compare Register 0 for PWM Output 0 and
PWM Output 1.
PWM0COM1
Compare Register 1 for PWM Output 0 and
PWM Output 1.
PWM0COM2
Compare Register 2 for PWM Output 0 and
PWM Output 1.
PWM0LEN
Frequency control for PWM Output 0 and PWM
Output 1.
PWM1COM0
Compare Register 0 for PWM Output 2 and
PWM Output 3.
PWM1COM1
Compare Register 1 for PWM Output 2 and
PWM Output 3.
PWM1COM2
Compare Register 2 for PWM Output 2 and
PWM Output 3.
PWM1LEN
Frequency control for PWM Output 2 and PWM
Output 3.
PWM2COM0
Compare Register 0 for PWM Output 4
PWM2COM1
Compare Register 1 for PWM Output 4
PWMCLRI
PWM interrupt clear.
In all modes, the PWMxCOMx MMRs control the point at
which the PWM outputs change state. An example of the first
pair of PWM outputs (PWM0 and PWM1) is shown in Figure 40.
HIGH SIDE
(PWM0)
LOW SIDE
(PWM1)
PWM0COM2
PWM0COM1
PWM0COM0
PWM0LEN
08675-
056
Figure 40. PWM Timing
The PWM clock is selectable via PWMCON1 with one of the
following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or
256. The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents, as shown with the
PWM0 and PWM1 waveforms in Figure 40.
The low-side waveform, PWM1, goes high when the timer
count reaches PWM0LEN, and it goes low when the timer
count reaches the value held in PWM0COM2 or when the
high-side waveform (PWM0) goes low.
The high-side waveform, PWM0, goes high when the timer
count reaches the value held in PWM0COM0, and it goes low
when the timer count reaches the value held in PWM0COM1.
PWMCON1 Control Register
Name:
PWMCON1
Address:
0xFFFF0F80
Default value:
0x0012
Access:
Read and write
Function:
This is a 16-bit MMR that configures the
PWM outputs.
Rev. E
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