I2C REGISTERS The I" />
參數(shù)資料
型號(hào)： ADUC7023BCP6Z62IRL
廠商： Analog Devices Inc
文件頁數(shù)： 57/96頁
文件大?。?/td> 0K
描述： IC MCU 12BIT 62KB FLASH 40LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： I²C，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12 x12b; D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7023
Data Sheet
| Page 60 of 96
I2C REGISTERS
The I2C peripheral interfaces consists of a number of MMRs. These are described in the following section.
I2C Master Registers
I2C Master Control Registers, I2CxMCON
Name:
I2C0MCON, I2C1MCON
Address:
0xFFFF0800, 0xFFFF0900
Default value:
0x0000, 0x0000
Access:
Read/write
Function:
These 16-bit MMRs configure the I2C peripheral in master mode.
Table 65. I2CxMCON MMR Bit Designations
Bit
Name
Description
15 to 9
Reserved. These bits are reserved and should not be written to.
8
I2CMCENI
I2C transmission complete interrupt enable bit.
This bit is set to enable an interrupt on detecting a stop condition on the I2C bus.
This bit clears this interrupt source.
7
I2CNACKENI
I2C no acknowledge received interrupt enable bit.
This bit is set to enable interrupts when the I2C master receives a no acknowledge.
This bit clears this interrupt source.
6
I2CALENI
I2C arbitration lost interrupt enable bit.
This bit is set to enable interrupts when the I2C master has lost in trying to gain control of the I2C bus.
This bit clears this interrupt source.
5
I2CMTENI
I2C transmit interrupt enable bit.
This bit is set to enable interrupts when the I2C master has transmitted a byte.
This bit clears this interrupt source.
4
I2CMRENI
I2C receive interrupt enable bit.
This bit is set to enable interrupts when the I2C master receives data.
This bit is cleared by the user to disable interrupts when the I2C master is receiving data.
3
I2CMSEN
I2C master SCL stretch enable bit.
This bit is set to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low
until I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
This bit is cleared to disable clock stretching.
2
I2CILEN
I2C internal loopback enable bit.
This bit is set to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to
their respective input signals.
This bit is cleared by the user to disable loopback mode.
1
I2CBD
I2C master backoff disable bit.
This bit is set to allow the device to compete for control of the bus even if another device is currently driving a
start condition.
This bit is cleared to back off until the I2C bus becomes free.
0
I2CMEN
I2C master enable bit.
This bit is set by the user to enable I2C master mode.
This bit is cleared to disable I2C master mode.
Rev. E
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