- 您現(xiàn)在的位置：買賣IC網 > PDF目錄11209 > ADUC7023BCP6Z62IRL (Analog Devices Inc)IC MCU 12BIT 62KB FLASH 40LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADUC7023BCP6Z62IRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 55/96頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 12BIT 62KB FLASH 40LFCSP |
| 標準包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | I²C，SPI |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 20 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 12 x12b; D/A 4x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
Data Sheet
ADuC7023
| Page 59 of 96
I2C
The ADuC7023 incorporates two I2C peripherals that may be
configured as a fully I2C-compatible I2C bus master device or as
a fully I2C bus-compatible slave device.
The two pins used for data transfer, SDA and SCL, are configured
in a wire-AND format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are between 4.7 k and 10 k.
The I2C bus peripheral address in the I2C bus system is pro-
grammed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or/write) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges the data, transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I2C peripheral can only be configured as a master or slave
at any given time. The same I2C channel cannot simultaneously
support master and slave modes.
The I2C interface on the ADuC7023 includes support for
repeated start conditions. In master mode, the ADuC7023 can
be programmed to generate a repeated start. In slave mode, the
ADuC7023 recognizes repeated start conditions. In master and
slave mode, the part recognizes both 7-bit and 10-bit bus addresses.
In I2C master mode, the ADuC7023 supports continuous reads
from a single slave up to 512 bytes in a single transfer sequence.
Clock stretching is supported in both master and slave modes.
In slave mode, the ADuC7023 can be programmed to return a
NACK. This allows the validation of checksum bytes at the end
of I2C transfers. Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for I2C
hardware testing. In loopback mode. The transmit and receive
circuits in both master and slave mode contain 2-byte FIFOs.
Status bits are available to the user to control these FIFOs.
CONFIGURING EXTERNAL PINS FOR I2C
FUNCTIONALITY
The I2C pins of the ADuC7023 device are P0.4 and P0.5 for I2C0
and P0.6 and P0.7 for I2C1.
P0.4 and P0.6 are the I2C clock signals and P0.5 and P0.7 are the
I2C data signals. For instance, to configure I2C0 pins (SCL0,
SDA0), Bit 16 and Bit 20 of the GP0CON register must be set to
1 to enable I2C mode. On the other hand, to configure I2C1 pins
(SCL1, SDA1), Bit 25 and Bit 29 of the GP0CON register must
be set to 1 to enable I2C mode, as shown in the GPIO section.
I2C1 function is available at P0.6 and P0.7 on 32-lead and 36-
ball packages and available at P1.6 and P1.7 on 40-lead package.
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CDIV MMR as follows:
)
(2
)
2
(
DIVL
DIVH
+
=
UCLK
CLOCK
SERIAL
f
where:
fUCLK is the clock before the clock divider and the clock selected
by POWCON1 Bit 4 to Bit 0.
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Thus, for 100 kHz operation,
DIVH = DIVL = 0xCF
and for 400 kHz,
DIVH = 0x28, DIVL = 0x3C
The I2CDIV register corresponds to DIVH:DIVL.
I2C BUS ADDRESSES
Slave Mode
In slave mode, the registers I2CxID0, I2CxID1, I2CxID2, and
I2CxID3 contain the device IDs. The device compares the four
I2CxIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7MSBs of either ID
register must be identical to that of the 7MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
The ADuC7023 also supports 10-bit addressing mode. When
Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in registers
I2CxID0 and I2CxID1. The 10-bit address is derived as follows:
I2CxID0[0] is the read/write bit and is not part of the I2C
address.
I2CxID0[7:1] = Address Bits[6:0].
I2CxID1[2:0] = Address Bits[9:7].
I2CxID1[7:3] must be set to 11110b.
Master Mode
In master mode, the I2CxADR0 register is programmed with
the I2C address of the device.
In 7-bit address mode, I2CxADR0[7:1] are set to the device
address. I2CxADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CxADR0[7:3] must be set to 11110b.
I2CxADR0[2:1] = Address Bits[9:8].
I2CxADR1[7:0] = Address Bits[7:0].
I2CxADR0[0] is the read/write bit.
Rev. E
相關PDF資料 |
PDF描述 |
|---|---|
| ADUC7023BCPZ62I-RL | IC MCU 12BIT 62KB FLASH 32LFCSP |
| ATMEGA32L-8MUR | MCU AVR 32K FLASH 8MHZ 44QFN |
| ATMEGA32-16MUR | MCU AVR 32KB FLASH 16MHZ 44QFN |
| ADG528ATQ | IC MULTIPLEXER 8X1 18CDIP |
| AD7511DIKNZ | IC SWITCH QUAD SPST 16DIP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC7023BCPZ62I | 功能描述:IC MCU 12BIT 62KB FLASH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標準包裝:250 系列:LPC11Uxx 核心處理器:ARM? Cortex?-M0 芯體尺寸:32-位 速度:50MHz 連通性:I²C，Microwire，SPI，SSI，SSP，UART/USART，USB 外圍設備:欠壓檢測/復位，POR，WDT 輸入/輸出數(shù):40 程序存儲器容量:96KB（96K x 8） 程序存儲器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉換器:A/D 8x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-LQFP 包裝:托盤 其它名稱:568-9587 |
| ADUC7023BCPZ62I-R7 | 功能描述:IC MCU 12BIT 62KB FLASH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC7023BCPZ62I-RL | 功能描述:IC MCU 12BIT 62KB FLASH 32LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC7024 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| ADUC7024BCP62 | 制造商:Analog Devices 功能描述:FLASH ARM7+10-CH,12-B ADC &2X12-B DAC IC - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。