參數(shù)資料
型號： ADUC7023BCP6Z62IRL
廠商： Analog Devices Inc
文件頁數(shù)： 62/96頁
文件大?。?/td> 0K
描述： IC MCU 12BIT 62KB FLASH 40LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： I²C，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12 x12b; D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7023
| Page 65 of 96
Table 73. I2CxSSTA MMR Bit Designations
Bit
Name
Description
15
Reserved bit.
14
I2CSTA
This bit is set to 1 if: A start condition followed by a matching address is detected. It is also set if a start
byte (0x01) is received. If general calls are enabled and a general call code of (0x00) is received.
This bit is cleared on receiving a stop condition.
13
I2CREPS
This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition.
12 to 11
I2CID[1:0]
I2C address matching register. These bits indicate which I2CxIDx register matches the received address.
[00] = received address matches I2CxID0.
[01] = received address matches I2CxID1.
[10] = received address matches I2CxID2.
[11] = received address matches I2CxID3.
10
I2CSS
I2C stop condition after start detected bit.
This bit is set to 1 when a stop condition is detected after a previous start and matching address.
When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated.
This bit is cleared by reading this register.
9 to 8
I2CGCID[1:0]
I2C general call ID bits.
[00] = no general call received.
[01] = general call reset and program address.
[10] = general program address.
[11] = general call matching alternative ID.
These bits are not cleared by a general call reset command.
These bits are cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON.
7
I2CGC
I2C general call status bit.
This bit is set to 1 if the slave receives a general call command of any type. If the command received is a
reset command, then all registers return to their default state. If the command received is a hardware
general call, the Rx FIFO holds the second byte of the command, and this can be compared with the
I2CxALT register.
This bit is cleared by writing a 1 to the I2CGCCLR bit in I2CxSCON.
6
I2CSBUSY
I2C slave busy status bit.
This bit is set to 1 when the slave receives a start condition.
This bit is cleared by hardware if the received address does not match any of the I2CxIDx registers, the
slave device receives a stop condition or if a repeated start address does not match any of the I2CxIDx
registers.
5
I2CSNA
I2C slave no acknowledge data bit.
This bit is set to 1 when the slave responds to a bus address with a no acknowledge. This bit is asserted
under the following conditions: if no acknowledge is returned because there is no data in the Tx FIFO or if
the I2CNACKEN bit is set in the I2CxSCON register.
This bit is cleared in all other conditions.
4
I2CSRxFO
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
3
I2CSRXQ
I2C slave receive request bit.
This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur if the
I2CSRXENI bit in I2CxSCON is set.
The Rx FIFO must be read or flushed to clear this bit.
2
I2CSTXQ
I2C slave transmit request bit.
This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in
I2CxSCON is = 0, , this bit goes high just after the negative edge of SCL during the read bit transmission. If
the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the read
bit transmission. This bit causes an interrupt to occur if the I2CSTXENI bit in I2CxSCON is set.
This bit is cleared in all other conditions.
Rev. E
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