參數(shù)資料
型號: ADT7476ARQZ-REEL7
廠商: ANALOG DEVICES INC
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 10BIT(s), 2.50Cel, RECTANGULAR, SURFACE MOUNT
封裝: ROHS COMPLIANT, MO-137AE, QSOP-24
文件頁數(shù): 28/72頁
文件大?。?/td> 5219K
代理商: ADT7476ARQZ-REEL7
ADT7476
Rev. B | Page 34 of 72
The fan counter does not count the fan TACH output pulses
directly because the fan speed could be less than 1000 RPM and
it takes several seconds to accumulate a reasonably large and
accurate count. Instead, the period of the fan revolution is
measured by gating an on-chip 90 kHz oscillator into the input
of a 16-bit counter for N periods of the fan TACH output
(Figure 45). Therefore, the accumulated count is actually
proportional to the fan tachometer period and inversely
proportional to the fan speed.
N, the number of pulses counted, is determined by the settings
of TACH pulses per revolution register (0x7B). This register
contains two bits for each fan, allowing one, two (default), three,
or four TACH pulses to be counted.
05382-046
1
2
3
4
CLOCK
PWM
TACH
Figure 45. Fan Speed Measurement
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a
2-byte read from the ADT7476.
Register 0x28, TACH1 Low Byte = 0x00 default
Register 0x29, TACH1 High Byte = 0x00 default
Register 0x2A, TACH2 Low Byte = 0x00 default
Register 0x2B, TACH2 High Byte = 0x00 default
Register 0x2C, TACH3 Low Byte = 0x00 default
Register 0x2D, TACH3 High Byte = 0x00 default
Register 0x2E, TACH4 Low Byte = 0x00 default
Register 0x2F, TACH4 High Byte = 0x00 default
Reading Fan Speed from the ADT7476
The measurement of fan speeds involves a 2-register read for
each measurement. The low byte should be read first. This
causes the high byte to be frozen until both high and low byte
registers are read, preventing erroneous TACH readings. The
fan tachometer reading registers report back the number of
11.11 μs period clocks (90 kHz oscillator) gated to the fan speed
counter, from the rising edge of the first fan TACH pulse to the
rising edge of the third fan TACH pulse (assuming two pulses
per revolution are being counted).
Because the device is essentially measuring the fan TACH
period, the higher the count value, the slower the fan is actually
running. A 16-bit fan tachometer reading of 0xFFFF indicates
that the fan has stalled or is running very slowly (<100 RPM).
High Limit > Comparison Performed
Because the actual fan TACH period is being measured, falling
below a fan TACH limit by 1 sets the appropriate status bit and
can be used to generate an SMBALERT.
Measuring fan TACH has the following caveat: when the
ADT7476 starts up, TACH measurements are locked. In effect,
an internal read of the low byte has been made for each TACH
input. The net result of this is that all TACH readings are
locked until the high byte is read from the corresponding
TACH registers. All TACH-related interrupts are also ignored
until the appropriate high byte is read.
Once the corresponding high byte is read, TACH measure-
ments are unlocked and interrupts are processed as normal.
Fan TACH Limit Registers
The fan TACH limit registers are 16-bit values consisting of
two bytes.
Register 0x54, TACH1 Minimum Low Byte = 0xFF default
Register 0x55, TACH1 Minimum High Byte = 0xFF default
Register 0x56, TACH2 Minimum Low Byte = 0xFF default
Register 0x57, TACH2 Minimum High Byte = 0xFF default
Register 0x58, TACH3 Minimum Low Byte = 0xFF default
Register 0x59, TACH3 Minimum High Byte = 0xFF default
Register 0x5A, TACH4 Minimum Low Byte = 0xFF default
Register 0x5B, TACH4 Minimum High Byte = 0xFF default
Fan Speed Measurement Rate
The fan TACH readings are normally updated once every second.
The FAST bit (Bit 3) of Configuration Register 3 (0x78), when
set, updates the fan TACH readings every 250 ms.
DC Bits
If any fans are not driven by a PWM channel but are powered
directly from 5 V or 12 V, their associated dc bit in Configur-
ation Register 3 should be set. This allows TACH readings to be
taken on a continuous basis for fans connected directly to a dc
source. For 4-wire fans, once high frequency mode is enabled,
the dc bits do not need to be set because this is automatically
done internally.
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