參數(shù)資料
型號(hào)： ADT7476ARQZ-REEL7
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 10BIT(s), 2.50Cel, RECTANGULAR, SURFACE MOUNT
封裝： ROHS COMPLIANT, MO-137AE, QSOP-24
文件頁(yè)數(shù)： 22/72頁(yè)
文件大?。?/td> 5219K
代理商： ADT7476ARQZ-REEL7
ADT7476
Rev. B | Page 29 of 72
THERM
TIMER
(REG. 0x79)
THERM ASSERTED
≤ 22.76ms
76 5
321 0
4
00 0
000 1
0
THERM
TIMER
(REG. 0x79)
THERM ASSERTED
≥ 45.52ms
76 5
321 0
4
00 0
001 0
0
THERM
TIMER
(REG. 0x79)
THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
76 5
321 0
4
00 0
010 1
0
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
05
38
2-
03
3
2.
Bit 0 of the THERM timer is set to 1 because a THERM
assertion is occurring. The THERM timer increments
from zero.
3.
If the THERM timer limit (Reg. 0x7A) = 0x00, the F4P bit
is set.
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7476 can generate an SMBALERT when a
programmable THERM timer limit is exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions
while capturing longer THERM timer events. Register 0x7A is
the THERM timer limit register. This 8-bit register allows a
limit from 0 seconds (first THERM assertion) to 5.825 seconds
to be set before an SMBALERT is generated. The THERM timer
value is compared with the contents of the THERM timer limit
register. If the THERM timer value exceeds the THERM timer
limit value, then the F4P bit (Bit 5) of Interrupt Status Register 2
(0x42) is set and an SMBALERT is generated.
Figure 32. Understanding the THERM Timer
Note that, depending on which pins are configured as a THERM
timer, setting the F4P bit (Bit 5) of Interrupt Mask Register 2
(0x75) or Bit 0 of Interrupt Mask Register 1 (0x74) masks out
SMBALERT, although the F4P bit of Interrupt Status Register 2 is
still set if the THERM timer limit is exceeded.
When using the THERM timer, be aware of the following.
After a THERM timer read (Register 0x79):
1.
The contents of the timer are cleared on read.
2.
The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming that the THERM timer limit has been
exceeded).
Figure 33 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (0x7A) causes an SMBALERT to be
generated on the first THERM assertion. A THERM timer limit
value of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
If the THERM timer is read during a THERM assertion, the
following happens:
1.
The contents of the timer are cleared.
22.76ms
45.52ms
91.04ms
182.08ms
364.16ms
728.32ms
1.457s
2.914s
IN
OUT
RESET
LATCH
CLEARED
ON READ
F4P BIT (BIT 5)
MASK REGISTER 2
(REGISTER 0x75)
1 = MASK
F4P BIT (BIT 5)
STATUS REGISTER 2
COMPARATOR
22.76ms
45.52ms
91.04ms
182.08ms
364.16ms
728.32ms
1.457s
2.914s
7
6
5
4
3
2
1
0
7 6 543 2 1 0
THERM LIMIT
(REGISTER 0x7A)
THERM TIMER
(REGISTER 0x79)
THERM TIMER CLEARED ON READ
SMBALERT
THERM
05
382
-0
34
Figure 33. Functional Block Diagram of THERM Monitoring Circuitry
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