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參數(shù)資料
| 型號(hào)： | ADT7470ARQZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | DIGITAL TEMP SENSOR-SERIAL, 7BIT(s), RECTANGULAR, SURFACE MOUNT |
| 封裝： | ROHS COMPLIANT, MO-137AB, QSOP-16 |
| 文件頁數(shù)： | 4/40頁 |
| 文件大?。?/td> | 962K |
| 代理商： | ADT7470ARQZ |
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ADT7470
Rev. C | Page 12 of
40
2.
The master initiates a read operation and sends the alert
response address (ARA = 000 1100). This is a general call
address that must not be used as a specific device address.
READ OPERATIONS
The ADT7470 uses the following SMBus read protocols.
Receive Byte
3.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known, and it
can be interrogated in the usual way.
This is useful when repeatedly reading a single register.
The register address must be set up previously. In this
operation, the master device receives a single byte from
a slave device, as follows:
4.
If more than one device’s SMBALERT output is low,
the one with the lowest device address has priority,
in accordance with normal SMBus arbitration.
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by
the read bit (high).
5.
Once the ADT7470 responds to the alert response
address, the master must read the status registers,
and the SMBALERT is cleared only if the error condition
is gone.
3.
The addressed slave device asserts ACK on SDA.
4.
The master receives a data byte.
5.
The master asserts NO ACK on SDA.
SMBus TIMEOUT
6.
The master asserts a stop condition on SDA
and the transaction ends.
The ADT7470 includes an SMBus timeout feature. If there is no
SMBus activity for more than 31 ms, the ADT7470 assumes that
the bus is locked and releases the bus. This prevents the device
from locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
In the ADT7470, the receive byte protocol is used to read a
single byte of data from a register whose address was previously
set by a send byte or write byte operation.
12
3
4
5
6
S
R
A
DATA
A
P
SLAVE
ADDRESS
04684-0-012
Table 6. Configuration Register 1—Register 0x40
Bit Address and Value
Description
Bit 3 TODIS = 0
SMBus timeout enabled (default).
Bit 3 TODIS = 1
SMBus timeout disabled.
Figure 12. Single-Byte Write from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices,
which allows an interrupting device to identify itself to the host
when multiple devices exist on the same bus.
Although the ADT7470 supports packet error checking (PEC),
its use is optional. It is triggered by supplying the extra clock
for the PEC byte. The PEC byte is calculated using CRC-8.
The frame check sequence (FCS) conforms to CRC-8 by the
following polynomial:
The SMBALERT output can be used as an interrupt output
or can be used as an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
occurs:
C(x) = x8 + x2 + x1 + 1
Consult the SMBus 1.1 Specification for more information by
searching online.
1.
SMBALERT is pulled low.
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