參數(shù)資料
型號(hào)： ADT7470ARQZ
廠商： ANALOG DEVICES INC
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 7BIT(s), RECTANGULAR, SURFACE MOUNT
封裝： ROHS COMPLIANT, MO-137AB, QSOP-16
文件頁數(shù)： 11/40頁
文件大?。?/td> 962K
代理商： ADT7470ARQZ
ADT7470
Rev. C | Page 19 of
40
Masking Interrupt Sources
Interrupt Mask Register 1 and Interrupt Mask Register 2 are
located at Address 0x72 and Address 0x73. These allow indi-
vidual interrupt sources to be masked out to prevent unwanted
SMBALERT interrupts. Masking an interrupt source prevents
only the SMBALERT output from being asserted; the appro-
priate status bit is still set as usual. This is useful if the system
polls the monitoring devices periodically to determine whether
or not out-of-limit conditions have subsided, without tying up
time-critical system resources.
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt output is a dedicated function pro-
vided on Pin 14 to signal out-of-limit conditions to a host or
system processor. Because this is a dedicated function, it is
important that limit registers be programmed before monitoring
is enabled to prevent spurious interrupts from occurring on the
SMBALERT pin. Although the SMBALERT output cannot be
specifically disabled, interrupt sources can be masked to prevent
SMBALERT assertions. Monitoring is enabled when Bit 0 (STRT)
of Configuration Register 1 (Register 0x40) is set to 1.
Table 14. Interrupt Mask Register 1 (Register 0x72)
Bit No.
Mnemonic
Description
7
Unused
Unused.
6
R7T
A 1 masks the SMBALERT for TMP05 Temperature 7.
5
R6T
A 1 masks the SMBALERT for TMP05 Temperature 6.
4
R5T
A 1 masks the SMBALERT for TMP05 Temperature 5.
3
R4T
A 1 masks the SMBALERT for TMP05 Temperature 4.
2
R3T
A 1 masks the SMBALERT for TMP05 Temperature 3.
1
R2T
A 1 masks the SMBALERT for TMP05 Temperature 2.
0
R1T
A 1 masks the SMBALERT for TMP05 Temperature 1.
Table 15. Interrupt Mask Register 2 (Register 0x73)
Bit No.
Mnemonic
Description
7
Fan 4
A 1 masks the SMBALERT for Fan 4 overspeed/underspeed conditions.
6
Fan 3
A 1 masks the SMBALERT for Fan 3 overspeed/underspeed conditions.
5
Fan 2
A 1 masks the SMBALERT for Fan 2 overspeed/underspeed conditions.
4
Fan 1
A 1 masks the SMBALERT for Fan 1 overspeed/underspeed conditions.
3
Unused
Unused.
2
R10T
A 1 masks the SMBALERT for TMP05 Temperature 10.
1
R9T
A 1 masks the SMBALERT for TMP05 Temperature 9.
0
R8T
A 1 masks the SMBALERT for TMP05 Temperature 8.
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