參數(shù)資料
型號(hào)： ADSP-TS203SABPZ050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁(yè)數(shù)： 8/48頁(yè)
文件大?。?/td> 2017K
代理商： ADSP-TS203SABPZ050
Rev. C
|
Page 16 of 48
|
December 2006
ADSP-TS203S
Table 9. Pin Definitions—JTAG Port
Signal
Type
Term
Description
EMU
O/OD
nc
1
Emulation. Connected to the DSP’s JTAG emulator target board connector only.
TCK
I
epd or epu
Test Clock (JTAG). Provides an asynchronous clock for JTAG scan.
TDI
I
(pu_ad)
nc
Test Data Input (JTAG). A serial data input of the scan path.
TDO
O/T
nc1
Test Data Output (JTAG). A serial data output of the scan path.
TMS
I
(pu_ad)
nc1
Test Mode Select (JTAG). Used to control the test state machine.
TRST
I/A
(pu_ad)
na
Test Reset (JTAG). Resets the test state machine. TRST must be asserted or pulsed low
after power-up for proper device operation. For more information, see Reset and
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω to VSS; epu = external pull-up approx-
imately 5 k
Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS
1 See the reference on Page 11 to the JTAG emulation technical reference EE-68.
Table 10. Pin Definitions—Flags, Interrupts, and Timer
Signal
Type
Term
Description
FLAG3–0
I/O/A
(pu)
nc
FLAG pins. Bidirectional input/output pins can be used as program conditions. Each pin
can be configured individually for input or for output. FLAG3–0 are inputs after power-up
and reset.
IRQ3–0
I/A
(pu)
nc
Interrupt Request. When asserted, the DSP generates an interrupt. Each of the IRQ3–0 pins
can be independently set for edge-triggered or level-sensitive operation. After reset, these
pins are disabled unless the IRQ3–0 strap option and interrupt vectors are initialized for
booting.
TMR0E
O
na
Timer 0 expires. This output pulses whenever timer 0 expires. At reset, this is a strap pin.
For more information, see Table 16 on Page 19.
I = input; A = asynchronous; O = output; OD = open-drain output; T = three-state; P = power supply; G = ground; pd = internal pull-down
5k
Ω; pu = internal pull-up 5 kΩ; pd_0 = internal pull-down 5 kΩ on DSP ID = 0; pu_0 = internal pull-up 5 kΩ on DSP ID = 0; pu_od_0 = internal
pull-up 500
Ω on DSP ID = 0; pd_m = internal pull-down 5 kΩ on DSP bus master; pu_m = internal pull-up 5 kΩ on DSP bus master; pu_ad
= internal pull-up 40 k
Ω. For more pull-down and pull-up information, see Electrical Characteristics on Page 21.
Term (termination of unused pins) column symbols: epd = external pull-down approximately 5 k
Ω to VSS; epu = external pull-up approx-
imately 5 k
Ω to VDD_IO, nc = not connected; na = not applicable (always used); VDD_IO = connect directly to VDD_IO; VSS = connect directly to VSS
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