參數(shù)資料
型號(hào)： ADSP-TS203SABPZ050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁(yè)數(shù)： 46/48頁(yè)
文件大?。?/td> 2017K
代理商： ADSP-TS203SABPZ050
ADSP-TS203S
Rev. C
|
Page 7 of 48
|
December 2006
Host Interface
The ADSP-TS203S processor provides an easy and configurable
interface between its external bus and host processors through
the external port. To accommodate a variety of host processors,
the host interface supports pipelined or slow protocols for
ADSP-TS203S processor access of the host as slave or pipelined
for host access of the ADSP-TS203S processor as slave. Each
protocol has programmable transmission parameters, such as
idle cycles, pipe depth, and internal wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mecha-
nism. When the host asserts BOFF, the DSP backs off the
current transaction and asserts HBG and relinquishes the
external bus.
The host can directly read or write the internal memory of the
ADSP-TS203S processor, and it can access most of the DSP reg-
isters, including DMA control (TCB) registers. Vector
interrupts support efficient execution of host commands.
Multiprocessor Interface
The ADSP-TS203S processor offers powerful features tailored
to multiprocessing DSP systems through the external port and
link ports. This multiprocessing capability provides the highest
bandwidth for interprocessor communication, including
Up to eight DSPs on a common bus
On-chip arbitration for glueless multiprocessing
Link ports for point-to-point communication
The external port and link ports provide integrated, glueless
multiprocessing support.
The external port supports a unified address space (see Figure 3)
that enables direct interprocessor accesses of each ADSP-
TS203S processor’s internal memory and registers. The DSP’s
on-chip distributed bus arbitration logic provides simple, glue-
less connection for systems containing up to eight
ADSP-TS203S processors and a host processor. Bus arbitration
has a rotating priority. Bus lock supports indivisible read-
modify-write sequences for semaphores. A bus fairness feature
prevents one DSP from holding the external bus too long.
The DSP’s two link ports provide a second path for interproces-
sor communications with throughput of 1G byte per second.
The cluster bus provides 500M bytes per second throughput—
with a total of 1.5G bytes per second interprocessor bandwidth.
SDRAM Controller
The SDRAM controller controls the ADSP-TS203S processor’s
transfers of data to and from external synchronous DRAM
(SDRAM) at a throughput of 32 bits per SCLK cycle using the
external port and SDRAM control pins.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16M bits, 64M bits, 128M bits, 256M bits and
512M bits. The DSP supports directly a maximum of four banks
of 64M words
× 32 bits of SDRAM. The SDRAM interface is
mapped in external memory in each DSP’s unified
memory map.
EPROM Interface
The ADSP-TS203S processor can be configured to boot from an
external 8-bit EPROM at reset through the external port. An
automatic process (which follows reset) loads a program from
the EPROM into internal memory. This process uses 16 wait
cycles for each read access. During booting, the BMS pin func-
tions as the EPROM chip select signal. The EPROM boot
procedure uses DMA Channel 0, which packs the bytes into
32-bit instructions. Applications can also access the EPROM
(write flash memories) during normal operation through DMA.
The EPROM or flash memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (24 address bits). The EPROM or
flash memory interface can be used after boot via a DMA.
DMA CONTROLLER
The ADSP-TS203S processor’s on-chip DMA controller, with
10 DMA channels, provides zero-overhead data transfers with-
out processor intervention. The DMA controller operates
independently and invisibly to the DSP’s core, enabling DMA
operations to occur while the DSP’s core continues to execute
program instructions.
The DMA controller performs DMA transfers between internal
memory, external memory, and memory-mapped peripherals;
the internal memory of other DSPs on a common bus, a host
processor, or link port I/O; between external memory and exter-
nal peripherals or link port I/O; and between an external bus
master and internal memory or link port I/O. The DMA con-
troller performs the following DMA operations:
External port block transfers. Four dedicated bidirectional
DMA channels transfer blocks of data between the DSP’s
internal memory and any external memory or memory-
mapped peripheral on the external bus. These transfers
support master mode and handshake mode protocols.
Link port transfers. Four dedicated DMA channels (two
transmit and two receive) transfer quad-word data only
between link ports and between a link port and internal or
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the two
receive channels.
AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
The DMA controller provides these additional features:
Flyby transfers. Flyby operations only occur through the
external port (DMA channel 0) and do not involve the
DSP’s core. The DMA controller acts as a conduit to
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