參數(shù)資料
型號： ADSP-TS203SABPZ050
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind
中文描述： 32-BIT, 125 MHz, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, BGA-576
文件頁數(shù)： 13/48頁
文件大?。?/td> 2017K
代理商： ADSP-TS203SABPZ050
Rev. C
|
Page 20 of 48
|
December 2006
ADSP-TS203S
ADSP-TS203S—SPECIFICATIONS
Note that component specifications are subject to change with
out notice. For information on link port electrical characteris-
OPERATING CONDITIONS
Parameter Description
Test Conditions
Grade1
1 Specifications vary for different grades (for example, SABP-060, SABP-050, SWBP-050). For more information on part grades, see Ordering Guide on Page 45.
Min
Typ
Max
Unit
VDD
Internal Supply Voltage
@ CCLK = 500 MHz
050
1.00
1.05
1.10
V
VDD_A
Analog Supply Voltage
@ CCLK = 500 MHz
050
1.00
1.05
1.10
V
VDD_IO
I/O Supply Voltage
(all)
2.38
2.50
2.63
V
VDD_DRAM
Internal DRAM Supply Voltage
@ CCLK = 500 MHz
050
1.425
1.500
1.575
V
TCASE
Case Operating Temperature
A
–40
+85
°C
VIH1
High Level Input Voltage2, 3
2 V
IH1 specification applies to input and bidirectional pins: SCLKRAT2–0, SCLK, ADDR31–0, DATA63–0, RD, WRL, ACK, BRST, BR7–0, BOFF, HBR, HBG, MSSD3–0, RAS,
CAS, SDCKE, SDWE, TCK, FLAG3–0, DS2–0, ENEDREG.
3 Values represent dc case. During transitions, the inputs may overshoot or undershoot to the voltage shown in Table 18, based on the transient duty cycle. The dc case is equivalent
to 100% duty cycle.
@ VDD, VDD_IO = Max
(all)
1.7
3.63
V
VIH2
High Level Input Voltage
3, 4
4 V
IH2 specification applies to input and bidirectional pins: TDI, TMS, TRST, CIMP1–0, ID2–0, LxBCMPI, LxACKI, POR_IN, RST_IN, IRQ3–0, CPA, DPA, DMAR3–0.
@ VDD, VDD_IO = Max
(all)
1.9
3.63
V
VIL
Low Level Input Voltage
3, 5
5 Applies to input and bidirectional pins.
@ VDD, VDD_IO = Min
(all)
–0.33
+0.8
V
IDD
VDD Supply Current, Typical Activity
6
6 For details on internal and external power calculation issues, including other operating conditions, see the EE-170, Estimating Power for the ADSP-TS203S on the Analog Devices
website.
@ CCLK = 500 MHz, VDD = 1.05 V, TCASE = 25°C
050
2.06
A
IDD_A
VDD_A Supply Current, Typical Activity
@ CCLK = 500 MHz, VDD = 1.05 V, TCASE = 25°C
050
20
50
mA
IDD_IO
VDD_IO Supply Current, Typical Activity
6
@ SCLK = 62.5 MHz, VDD_IO = 2.5 V, TCASE = 25°C
(all)
0.15
A
IDD_DRAM
VDD_DRAM Supply Current,
Typical Activity
6
@ CCLK = 500 MHz, VDD_DRAM = 1.5 V, TCASE = 25°C 050
0.25
0.40
A
VREF
Voltage Reference
(all)
(VDD_IO ×0.56)±5%
V
SCLK_VREF
Voltage Reference
(all)
(V
CLOCK
_DRIVE × 0.56) ±5%
V
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