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| 型號： | ADSP-2191MBCA-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 47/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144MBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SPI，SSP，UART |
| 時(shí)鐘速率： | 140MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 160kB |
| 電壓 - 輸入/輸出： | 3.00V，3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 144-迷你型BGA |
| 包裝： | 托盤 |
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ADSP-2191M
–8–
REV. A
Host can directly access the DSP’s entire memory space map,
boot memory space, and internal I/O space. To access the DSP’s
internal memory space, a Host steals one cycle per access from
the DSP. A Host access to the DSP’s external memory uses the
external port interface and does not stall (or steal cycles from)
the DSP’s core. Because a Host can access internal I/O memory
space, a Host can control any of the DSP’s I/O mapped
peripherals.
The Host port is most efficient when using the DSP as a slave
and uses DMA to automate the incrementing of addresses for
these accesses. In this case, an address does not have to be trans-
ferred from the Host for every data transfer.
Host Port Acknowledge (HACK) Modes
The Host port supports a number of modes (or protocols) for
generating a HACK output for the host. The host selects ACK
or Ready modes using the HACK_P and HACK pins. The Host
port also supports two modes for address control: Address Latch
Enable (ALE) and Address Cycle Control (ACC) modes. The
DSP auto-detects ALE versus ACC mode from the HALE and
HWR inputs.
The Host port HACK signal polarity is selected (only at reset) as
active high or active low, depending on the value driven on the
HACK_P pin.The HACK polarity is stored into the Host port
configuration register as a read only bit.
The DSP uses HACK to indicate to the Host when to complete
an access. For a read transaction, a Host can proceed and
complete an access when valid data is present in the read buffer
and the Host port is not busy doing a write. For a write transac-
tions, a Host can complete an access when the write buffer is not
full and the Host port is not busy doing a write.
Two mode bits in the Host Port configuration register HPCR
[7:6] define the functionality of the HACK line. HPCR6 is ini-
tialized at reset based on the values driven on HACK and
HACK_P pins (shown in Table 5); HPCR7 is always cleared (0)
at reset. HPCR [7:6] can be modified after reset by a write access
to the Host port configuration register.
The functional modes selected by HPCR [7:6] are as follows
(assuming active high signal):
ACK Mode—Acknowledge is active on strobes; HACK
goes high from the leading edge of the strobe to indicate
when the access can complete. After the Host samples the
HACK active, it can complete the access by removing the
strobe.The Host port then removes the HACK.
Ready Mode—Ready active on strobes, goes low to insert
waitstate during the access.If the Host port cannot
complete the access, it deasserts the HACK/READY line.
In this case, the Host has to extend the access by keeping
the strobe asserted. When the Host samples the HACK
asserted, it can then proceed and complete the access by
deasserting the strobe.
While in Address Cycle Control (ACC) mode and the ACK or
Ready acknowledge modes, the HACK is returned active for any
address cycle.
Host Port Chip Selects
There are two chip-select signals associated with the Host port:
HCMS and HCIOMS. The Host Chip Memory Select (HCMS)
lets the Host select the DSP and directly access the DSP’s inter-
nal/external memory space or boot memory space. The Host
Chip I/O Memory Select (
HCIOMS) lets the Host select the
DSP and directly access the DSP’s internal I/O memory space.
Before starting a direct access, the Host configures Host port
interface registers, specifying the width of external data bus
(8- or 16-bit) and the target address page (in the IJPG register).
The DSP generates the needed memory select signals during the
access, based on the target address. The Host port interface
combines the data from one, two, or three consecutive Host
accesses (up to one 24-bit value) into a single DMA bus access
to prefetch Host direct reads or to post direct writes. During
assembly of larger words, the Host port interface asserts ACK for
each byte access that does not start a read or complete a write.
Otherwise, the Host port interface asserts ACK when it has
completed the memory access successfully.
DSP Serial Ports (SPORTs)
The ADSP-2191M incorporates three complete synchronous
serial ports (SPORT0, SPORT1, and SPORT2) for serial and
multiprocessor communications. The SPORTs support the
following features:
Bidirectional operation—each SPORT has independent
transmit and receive pins.
Double-buffered transmit and receive ports—each port
has a data register for transferring data words to and from
memory and shift registers for shifting data in and out of
the data registers.
Clocking—each transmit and receive port can either use
an external serial clock (
40 MHz) or generate its own, in
frequencies ranging from 19 Hz to 40 MHz.
Word length—each SPORT supports serial data words
from 3 to 16 bits in length transferred in Big Endian
(MSB) or Little Endian (LSB) format.
Table 5. Host Port Acknowledge Mode Selection
Values Driven At
Reset
HPCR [7:6]
Initial Values
Acknowledge
Mode
HACK_P
HACK
Bit 7
Bit 6
0
1
Ready Mode
01
0
ACK Mode
10
0
ACK Mode
1
0
1
Ready Mode
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