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參數資料
| 型號： | ADSP-2191MBCA-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 3/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144MBGA |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，SPI，SSP，UART |
| 時鐘速率： | 140MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 160kB |
| 電壓 - 輸入/輸出： | 3.00V，3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA |
| 供應商設備封裝： | 144-迷你型BGA |
| 包裝： | 托盤 |
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–11–
REV. A
ADSP-2191M
Clock Signals
The ADSP-2191M can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors and a
1M
shunt resistor connected as shown in Figure 3. Capacitor
values are dependent on crystal type and should be specified by
the crystal manufacturer. A parallel-resonant, fundamental fre-
quency, microprocessor-grade crystal should be used for this
configuration.
If a buffered, shaped clock is used, this external clock connects
to the DSP’s CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. When an external clock is used, the XTAL
input must be left unconnected.
The DSP provides a user-programmable 1
to 32
multiplica-
tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
MSEL6–0, BYPASS, and DF pins decide the PLL multiplication
factor at reset. At runtime, the multiplication factor can be con-
trolled in software. The combination of pullup and pull-down
resistors in Figure 3 sets up a core clock ratio of 6:1, which
produces a 150 MHz core clock from the 25 MHz input. For
other clock multiplier settings, see the ADSP-219x/ADSP-2191
DSP Hardware Reference.
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-2191M operate at the rate
set by the peripheral clock. The peripheral clock is either equal
to the core clock rate or one-half the DSP core clock rate. This
selection is controlled by the IOSEL bit in the PLLCTL register.
The maximum core clock is 160 MHz and the maximum periph-
eral clock is 80 MHz—the combination of the input clock and
core/peripheral clock ratios may not exceed these limits.
Reset
The
RESET signal initiates a master reset of the ADSP-2191M.
The
RESET signal must be asserted during the powerup
sequence to assure proper initialization.
RESET during initial
powerup must be held long enough to allow the internal clock to
stabilize.
The powerup sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD is applied
to the processor, and for the internal phase-locked loop (PLL) to
lock onto the specific crystal frequency. A minimum of 100 s
ensures that the PLL has locked, but does not include the crystal
oscillator start-up time. During this powerup sequence the
RESET signal should be held low. On any subsequent resets, the
RESET signal must meet the minimum pulsewidth specifica-
tion, t
WRST.
The
RESET input contains some hysteresis. If using an RC
circuit to generate your
RESET signal, the circuit should use an
external Schmidt trigger.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and resets all registers to their
default values (where applicable). When
RESET is released, if
there is no pending bus request and the chip is configured for
booting, the boot-loading sequence is performed. Program
control jumps to the location of the on-chip boot ROM
(0xFF 0000).
Power Supplies
The ADSP-2191M has separate power supply connections for
the internal (V
DDINT) and external (VDDEXT) power supplies. The
internal supply must meet the 2.5 V requirement. The external
supply must be connected to a 3.3 V supply. All external supply
pins must be connected to the same supply.
Power-Up Sequence
Power up together the two supplies V
DDEXT and VDDINT. If they
cannot be powered up together, power up the internal (core)
supply first (powering up the core supply first reduces the risk of
latchup events.
Booting Modes
The ADSP-2191M has five mechanisms (listed in Table 6) for
automatically loading internal program memory after reset. Two
no-boot modes are also supported.
Figure 3. External Crystal Connections
CLKIN
CLKOUT
XTAL
ADSP-2196M
MSEL5 (PF5)
MSEL4 (PF4)
MSEL3 (PF3)
MSEL2 (PF2)
MSEL1 (PF1)
MSEL0 (PF0)
RESET
25MHz
MSEL6 (PF6)
DF (PF7)
VDD
BYPASS
RESET
SOURCE
RUNTIME
PF PIN I/O
THE PULL-UP/PULL-DOWN
RESISTORS ON THE MSEL,
DF, AND BYPASS PINS
SELECT THE CORE CLOCK
RATIO.
HERE, THE SELECTION (6:1)
AND 25MHz INPUT CLOCK
PRODUCE A 150MHz CORE
CLOCK.
1M
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