參數(shù)資料
型號(hào)： ADSP-2191MBCA-140
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 45/48頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 144MBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SPI，SSP，UART
時(shí)鐘速率： 140MHz
非易失內(nèi)存： 外部
芯片上RAM： 160kB
電壓 - 輸入/輸出： 3.00V，3.30V
電壓 - 核心： 2.50V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA
供應(yīng)商設(shè)備封裝： 144-迷你型BGA
包裝： 托盤
ADSP-2191M
–6–
REV. A
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer’s IJPG register to the
appropriate memory page.
The ADSP-2191M has 1K word of on-chip ROM that holds
boot routines. If peripheral booting is selected, the DSP starts
executing instructions from the on-chip boot ROM, which starts
the boot process from the selected peripheral. For more informa-
is located on Page 255 in the DSP’s memory space map.
External (Off-Chip) Memory
Each of the ADSP-2191M’s off-chip memory spaces has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, waitstate completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memory access strobe widths. For more information,
spaces are:
External memory space (MS3–0 pins)
I/O memory space (IOMS pin)
Boot memory space (BMS pin)
All of these off-chip memory spaces are accessible through the
External Port, which can be configured for data widths of
8 or 16 bits.
External Memory Space
External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0
containing Pages 1
63, Bank1 containing Pages 64127, Bank2
containing Pages 128
191, and Bank3 that contains Pages
192
254. The MS3–0 memory bank pins select Banks 3–0,
respectively. The external memory interface is byte-addressable
and decodes the 8 MSBs of the DSP program address to select
one of the four banks. Both the ADSP-219x core and DMA-capa-
ble peripherals can access the DSP’s external memory space.
I/O Memory Space
The ADSP-2191M supports an additional external memory
called I/O memory space. This space is designed to support
simple connections to peripherals (such as data converters and
external registers) or to bus interface ASIC data registers. I/O
space supports a total of 256K locations. The first 8K addresses
are reserved for on-chip peripherals. The upper 248K addresses
are available for external peripheral devices. The DSP’s instruc-
tion set provides instructions for accessing I/O space. These
instructions use an 18-bit address that is assembled from an
8-bit I/O page (IOPG) register and a 10-bit immediate value
supplied in the instruction. Both the ADSP-219x core and a Host
(through the Host Port Interface) can access I/O memory space.
Boot Memory Space
Boot memory space consists of one off-chip bank with 63 pages.
The
BMS memory bank pin selects boot memory space. Both
the ADSP-219x core and DMA-capable peripherals can access
the DSP’s off-chip boot memory space. After reset, the DSP
always starts executing instructions from the on-chip boot ROM.
Depending on the boot configuration, the boot ROM code can
start booting the DSP from boot memory. For more information,
Interrupts
The interrupt controller lets the DSP respond to 17 interrupts
with minimum overhead. The controller implements an interrupt
priority scheme as shown in Table 1. Applications can use the
unassigned slots for software and peripheral interrupts.
Table 2 shows the ID and priority at reset of each of the periph-
eral interrupts. To assign the peripheral interrupts a different
priority, applications write the new priority to their correspond-
ing control bits (determined by their ID) in the Interrupt Priority
Control register. The peripheral interrupt’s position in the
IMASK and IRPTL register and its vector address depend on its
priority level, as shown in Table 1. Because the IMASK and
IRPTL registers are limited to 16 bits, any peripheral interrupts
assigned a priority level of 11 are aliased to the lowest priority bit
position (15) in these registers and share vector address
0x00 01E0.
Table 1. Interrupt Priorities/Addresses
Interrupt
IMASK/
IRPTL
Vector
Address1
1These interrupt vectors start at address 0x10000 when the DSP is in
“no-boot,” run from external memory mode.
Emulator (NMI)—
Highest Priority
NA
Reset (NMI)
0
0x00 0000
Power-Down (NMI)
1
0x00 0020
Loop and PC Stack
2
0x00 0040
Emulation Kernel
3
0x00 0060
User Assigned Interrupt
4
0x00 0080
User Assigned Interrupt
5
0x00 00A0
User Assigned Interrupt
6
0x00 00C0
User Assigned Interrupt
7
0x00 00E0
User Assigned Interrupt
8
0x00 0100
User Assigned Interrupt
9
0x00 0120
User Assigned Interrupt
10
0x00 0140
User Assigned Interrupt
11
0x00 0160
User Assigned Interrupt
12
0x00 0180
User Assigned Interrupt
13
0x00 01A0
User Assigned Interrupt
14
0x00 01C0
User Assigned Interrupt—
Lowest Priority
15
0x00 01E0
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