參數(shù)資料
型號(hào)： ADSP-21366SBBCZENG
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： LEAD FREE, MO-205AE, MBGA-136
文件頁(yè)數(shù)： 23/54頁(yè)
文件大?。?/td> 559K
代理商： ADSP-21366SBBCZENG
ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 23 of 54
|
September 2004
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the Precision Clock Generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All Timing Param-
eters and Switching Characteristics apply to external DAI pins
(DAI_P07 – DAI_P20).
Table 18. Precision Clock Generator (Direct Pin Routing)
Parameter
Timing Requirement
s
t
PCGIW
t
STRIG
t
HTRIG
Min
Max
Unit
Input Clock Period
PCG Trigger Setup Before Falling Edge of PCG Input Clock
PCG Trigger Hold After Falling Edge of PCG Input Clock
24
2
2
ns
ns
Switching Characteristics
t
DPCGIO
PCG Output Clock and Frame Sync Active Edge Delay After
PCG Input Clock
PCG Output Clock and Frame Sync Delay After PCG Trigger
Output Clock Period
2.5
2.5 + 2.5 × t
PCGOW
10 + 2.5 × t
PCGOW
ns
48
10
ns
t
DTRIG
t
PCGOW
Figure 15. Precision Clock Generator (Direct Pin Routing)
DAI_Pn
PCG_TRIGx_I
t
STRIG
DAI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
PCG_CLKx_O
DAI_Pz
PCG_FSx_O
t
HTRIG
t
DPCGIO
t
DTRIG
t
PCGIW
t
PCGOW
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