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參數(shù)資料
| 型號： | ADSP-21366SBBCZENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | LEAD FREE, MO-205AE, MBGA-136 |
| 文件頁數(shù)： | 12/54頁 |
| 文件大?。?/td> | 559K |
| 代理商： | ADSP-21366SBBCZENG |
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Rev. PrA
|
Page 12 of 54
|
September 2004
ADSP-21365/6
Preliminary Technical Data
DAI_P20–1
I/O/T
(pu)
Three-state with
programmable
pullup
Digital Audio Interface Pins
. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the Serial ports, Input data port, precision clock gener-
ators and timers, sample rate converters and SPI to the DAI_P20–1 pins These pins
have internal 22.5 k
pullup resistors which are enabled on reset. These pullups can
be disabled in the DAI_PIN_PULLUP register.
Serial Peripheral Interface Clock Signal
. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of baud
rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active
during data transfers, only for the length of the transferred word. Slave devices ignore
the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted
out on one clock edge and sampled on the opposite edge of the clock. Clock polarity
and clock phase relative to data are programmable into the SPICTL control register
and define the transfer format. SPICLK has a 22.5 k
internal pullup resistor.
Serial Peripheral Interface Slave Device Select
. An active low signal used to select
the processor as an SPI slave device. This input signal behaves like a chip select, and
is provided by the master device for the slave devices. In multimaster mode the DSPs
SPIDS signal can be driven by a slave device to signal to the processor (as SPI master)
that an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multimaster error.
For a single-master, multiple-slave configuration where flag pins are used, this pin
must be tied or pulled high to V
DDEXT
on the master device. For ADSP-21365/6 to
ADSP-21365/6 SPI interaction, any of the master ADSP-21365/6's flag pins can be used
to drive the SPIDS signal on the ADSP-21365/6 SPI slave device.
SPI Master Out Slave In
. If the ADSP-21365/6 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21365/6
is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving
input data. In an ADSP-21365/6 SPI interconnection, the data is shifted out from the
MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI
has a 22.5 k
internal pullup resistor.
SPI Master In Slave Out
. If the ADSP-21365/6 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21365/6 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting
output data. In an ADSP-21365/6 SPI interconnection, the data is shifted out from the
MISO output pin of the slave and shifted into the MISO input pin of the master. MISO
has a 22.5 k
internal pullup resistor. MISO can be configured as O/D by setting the
OPD bit in the SPICTL register.
Note:
Only one slave is allowed to transmit data at any given time.
To enable broadcast
transmission to multiple SPI-slaves, the processor's MISO pin may be disabled by
setting (=1) bit 5 (DMISO) of the SPICTL register.
Boot Configuration Select
. This pin is used to select the boot mode for the processor.
The BOOTCFG pins must be valid before reset is asserted. See
Table 6
for a description
of the boot modes.
SPICLK
I/O
(pu)
Three-state with
pullup enabled
SPIDS
I
Input only
MOSI
I/O (O/D)
(pu)
Three-state with
pullup enabled
MISO
I/O (O/D)
(pu)
Three-state with
pullup enabled
BOOTCFG1–0
I
Input only
Table 3. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21366SBSQZENG | SHARC Processor |
| ADSP-21366SCSQZENG | SHARC Processor |
| ADSP-21366SKSQ-ENG | SHARC Processor |
| ADSP-21366SBBC-ENG | SHARC Processor |
| ADSP-2164BP-40 | SWITCH PB SPDT VERT .4VA SEALED |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21366SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21366SKBC-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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