參數(shù)資料
型號： ADSP-21366SKSQ-ENG
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝： MS-026BFB-HD, HSLQFP-144
文件頁數(shù)： 1/54頁
文件大小： 559K
代理商： ADSP-21366SKSQ-ENG
a
Preliminary Technical Data
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC
Processor
ADSP-21365/ADSP-21366
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Tel:781.329.4700
www.analog.com
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance automotive audio
processing
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Non-volatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES,
MPEG2 AAC, MPEG2 2channel, MP3, and functions like
Bass management, Delay, Speaker equalization, Graphic
equalization, and more. Decoder/post-processor algo-
rithm combination support will vary depending upon the
chip version and the system configurations. Please visit
www.analog.com/SHARC
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21365/6 is available with a 333 MHz core instruc-
tion rate and unique audio centric peripherals such as the
Digital Audio Interface, S/PDIF transceiver, DTCP (Digital
Content Transmission Protocol) available on the ADSP-
21365 only, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators and more. For
complete ordering information, see
Ordering Guide on
page 51
Figure 1. Functional Block Diagram – Processor Core
ADDR
DATA
IOD
ADDR
DATA
IOA
ADDR
DATA
IOA
SRAM
1M BIT
ROM
2M BIT
SRAM
0.5M BIT
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 3
ADDR
DATA
IOA
IOP REGISTERS
(MEMORY MAPPED)
SEE “ADSP-21365/6 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
I/O PROCESSOR
AND PERIPHERALS
6
JTAG TEST & EMULATION
32
PM ADDRESS BUS
DM ADDRESS BUS
32
PM DATA BUS
DM DATA BUS
64
64
PX REGISTER
PROCESSING
ELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
DAG1
8X4X32
DAG2
8X4X32
CORE PROCESSOR
PROGRAM
SEQUENCER
SRAM
1M BIT
ROM
2M BIT
SIGNAL
ROUTING
UNIT
SRAM
0.5M BIT
4 BLOCKS OF ON-CHIP MEMORY
IOD
IOA
IOD
IOD
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
S
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