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參數(shù)資料
| 型號(hào)： | ADSP-21362BBC-1AA |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 1320K |
| 代理商： | ADSP-21362BBC-1AA |
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Rev. A
|
Page 18 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
TIMING SPECIFICATIONS
The ADSP-2136x’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the processor’s internal clock frequency and
external (CLKIN) clock frequency with the CLKCFG1–0 pins
(see
Table 8 on Page 15
). To determine switching frequencies
for the serial ports, divide down the internal clock, using the
programmable divider control of each port (DIVx for the
serial ports).
The ADSP-2136x’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor’s internal clock (the
clock source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control shown in
Table 10
and
Table 11
.
Figure 6
shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2136x SHARC Processor Programming Reference
.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See
Figure 39 on Page 46
under Test Conditions for voltage
reference levels.
Timing Requirements
apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Switching Characteristics
specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Table 10. ADSP-2136x Clock Generation Operation
Timing
Requirements
CLKIN
CCLK
Description
Input Clock
Core Clock
Calculation
1/t
CK
1/t
CCLK
Table 11. Clock Periods
Timing
Requirements
t
CK
t
CCLK
t
PCLK
t
SCLK
t
SPICLK
Description
1
CLKIN Clock Period
(Processor) Core Clock Period
(Peripheral) Clock Period = 2 × t
CCLK
Serial Port Clock Period = (t
PCLK
) × SR
SPI Clock Period = (t
PCLK
) × SPIR
1
where:
SR = serial port-to-peripheral clock ratio (wide range, determined by SPORT
CLKDIV)
SPIR = SPI-to-peripheral clock ratio (wide range, determined by SPIBAUD
register)
DAI_Px = serial port clock
SPICLK = SPI clock
Figure 6. Core Clock and System Clock Relationship to CLKIN
DIVEN
÷2, 4, 8, 16
PLLM
DELAY
CCLK
(CORE CLOCK)
PLLICLK
XTAL
XTAL
OSC
CLKOUT
OR
RESETOUT
CLK_CFG [1:0]
(6:1, 16:1, 32:1)
PCLK
(PERIPHERAL CLOCK)
INDIV
÷1, 2
÷ 2
RESET
CLKIN
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| ADSP-21362BBCZ-1AA | SHARC Processor |
| ADSP-21362KBC-1AA | SHARC Processor |
| ADSP-21362KBCZ-1AA | SHARC Processor |
| ADSP-21362WBBCZ-1A | SHARC Processor |
| ADSP-21363BBC-1AA | SHARC Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21362BBCZ-1AA | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 333 MHz Processor includes DTCP/SPDIF RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| ADSP-21362BSWZ-1AA | 功能描述:IC DSP 32BIT 333MHZ EPAD 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21362KBC-1AA | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit/40-Bit 333MHz 333MIPS 136-Pin CSP-BGA |
| ADSP-21362KBCZ-1AA | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21362KSWZ-1AA | 制造商:Analog Devices 功能描述:IC SHARC DSP 333MHZ SMD LQFP144 |
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