參數(shù)資料
型號(hào)： ADSP-21362BBC-1AA
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁數(shù)： 13/52頁
文件大?。?/td> 1320K
代理商： ADSP-21362BBC-1AA
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Rev. A
|
Page 13 of 52
|
December 2006
SPICLK
I/O
(pu)
Three-state with
pull-up enabled
Serial Peripheral Interface Clock Signal
. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of baud
rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active
during data transfers, only for the length of the transferred word. Slave devices ignore
the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted
out on one clock edge and sampled on the opposite edge of the clock. Clock polarity
and clock phase relative to data are programmable into the SPICTL control register
and define the transfer format. SPICLK has a 22.5 k
Ω
internal pull-up resistor.
Serial Peripheral Interface Slave Device Select
. An active low signal used to select
the processor as an SPI slave device. This input signal behaves like a chip select, and
is provided by the master device for the slave devices. In multimaster mode the
processor’s SPIDS signal can be driven by a slave device to signal to the processor (as
SPI master) that an error has occurred, as some other device is also trying to be the
master device. If asserted low when the device is in master mode, it is considered a
multimaster error. For a single-master, multiple-slave configuration where flag pins
are used, this pin must be tied or pulled high to V
DDEXT
on the master device. For
processor to processor SPI interaction, any of the master processor’s flag pins can be
used to drive the SPIDS signal on the SPI slave device.
SPI Master Out Slave In
. If the ADSP-2136x is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the processor is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
data. In a SPI interconnection, the data is shifted out from the MOSI output pin of the
master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 k
Ω
internal
pull-up resistor.
SPI Master In Slave Out
. If the ADSP-2136x is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the processor is configured
as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output
data. In an SPI interconnection, the data is shifted out from the MISO output pin of the
slave and shifted into the MISO input pin of the master. MISO has a 22.5 k
Ω
internal
pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL
register.
Note:
Only one slave is allowed to transmit data at any given time.
To enable broadcast
transmission to multiple SPI-slaves, the processor’s MISO pin may be disabled by
setting (=1) Bit 5 (DMISO) of the SPICTL register.
Boot Configuration Select
. This pin is used to select the boot mode for the processor.
The BOOTCFG pins must be valid before reset is asserted. See
Table 7
for a description
of the boot modes.
Local Clock In
. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input.
It configures the ADSP-2136x to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the processors to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock input
depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or
operated below the specified frequency.
Crystal Oscillator Terminal
. Used in conjunction with CLKIN to drive an external
crystal.
Core/CLKIN Ratio Control
. These pins set the start up clock frequency. See
Table 8
for a description of the clock configuration modes. Note that the operating frequency
can be changed by programming the PLL multiplier and divider in the PMCTL register
at any time after the core comes out of reset.
SPIDS
I
Input only
MOSI
I/O (O/D)
(pu)
Three-state with
pull-up enabled
MISO
I/O (O/D)
(pu)
Three-state with
pull-up enabled
BOOTCFG1–0
I
Input only
CLKIN
I
Input only
XTAL
O
Output only
2
CLKCFG1–0
I
Input only
Table 4. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Description
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