參數(shù)資料
型號(hào)： ADSP-21362BBC-1AA
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁(yè)數(shù)： 12/52頁(yè)
文件大?。?/td> 1320K
代理商： ADSP-21362BBC-1AA
Rev. A
|
Page 12 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
PIN FUNCTION DESCRIPTIONS
The ADSP-2136x pin definitions are listed below. Inputs identi-
fied as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS and TDI).
Inputs identified as asynchronous (A) can be asserted asynchro-
nously to CLKIN (or to TCK for TRST). Tie or pull unused
inputs to V
DDEXT
or GND, except for the following:
DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,
and AD15–0 (NOTE: These pins have pull-up resistors.)
The following symbols appear in the Type column of
Table 4
:
A = asynchronous, G = ground, I = input, O = output,
P = power supply, S = synchronous, (A/D) = active drive,
(O/D) = open drain, and T = three-state, (pd) = pull-down resis-
tor, (pu) = pull-up resistor.
Table 4. Pin Descriptions
Pin
AD15–0
Type
I/O/T
(pu)
State During and
After Reset
Three-state with
pull-up enabled
Description
Parallel Port Address/Data.
The ADSP-2136x parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 k
Ω
internal pull-up resistor. See
Address/Data Modes on Page 15
for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper
16 external address bits, A23–8; ALE is used in conjunction with an external latch to
retain the values of the A23–8.
For detailed information on I/O operations and pin multiplexing, see the
ADSP-2136x
SHARC Processor Hardware Reference
.
Parallel Port Read Enable.
RD is asserted low whenever the processor reads 8-bit or
16-bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted. RD has a 22.5 k
Ω
internal pull-up resistor.
Parallel Port Write Enable.
WR is asserted low whenever the processor writes 8-bit or
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR has a 22.5 k
Ω
internal pull-up resistor.
Parallel Port Address Latch Enable.
ALE is asserted whenever the processor drives
a new address on the parallel port address pins. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this
pin remains deasserted. ALE has a 20 k
Ω
internal pull-down resistor.
Flag Pins.
Each flag pin is configured via control bits as either an input or output. As
an input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. For
detailed information on I/O operations and pin multiplexing, see the
ADSP-2136x
SHARC Processor Hardware Reference
.
Digital Audio Interface Pins
. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the serial ports, input data port, precision clock gener-
ators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins
have internal 22.5 k
Ω
pull-up resistors which are enabled on reset. These pull-ups can
be disabled in the DAI_PIN_PULLUP register.
RD
O
(pu)
Three-state, driven
high
1
WR
O
(pu)
Three-state, driven
high
1
ALE
O
(pd)
Three-state, driven
low
1
FLAG3–0
I/O/A
Three-state
DAI_P20–1
I/O/T
(pu)
Three-state with
programmable
pull-up
相關(guān)PDF資料
PDF描述
ADSP-21362BBCZ-1AA SHARC Processor
ADSP-21362KBC-1AA SHARC Processor
ADSP-21362KBCZ-1AA SHARC Processor
ADSP-21362WBBCZ-1A SHARC Processor
ADSP-21363BBC-1AA SHARC Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21362BBCZ-1AA 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 333 MHz Processor includes DTCP/SPDIF RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
ADSP-21362BSWZ-1AA 功能描述:IC DSP 32BIT 333MHZ EPAD 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21362KBC-1AA 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit/40-Bit 333MHz 333MIPS 136-Pin CSP-BGA
ADSP-21362KBCZ-1AA 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21362KSWZ-1AA 制造商:Analog Devices 功能描述:IC SHARC DSP 333MHZ SMD LQFP144
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*