參數(shù)資料
型號： ADSP-21160NKB-100
廠商： Analog Devices Inc
文件頁數(shù)： 3/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 32BIT 400BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標準包裝： 1
系列： SHARC®
類型： 浮點
接口： 主機接口，連接端口，串行端口
時鐘速率： 100MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.90V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤
–11–
REV. 0
ADSP-21160N
PAGE
O/T
DRAM Page Boundary. The ADSP-21160N asserts this pin to an external DRAM
controller, to signal that an external DRAM page boundary has been crossed. DRAM
page size must be defined in the ADSP-21160N’s memory control register (WAIT).
DRAM can only be implemented in external memory Bank 0; the PAGE signal can only
be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the
bus master. A keeper latch on the DSP’s PAGE pin maintains the output at the level it
was last driven (only enabled on the ADSP-21160N with ID2–0 = 00x).
BRST
I/O/T
Sequential Burst Access. BRST is asserted by ADSP-21160N or a host to indicate that
data associated with consecutive addresses is being read or written. A slave device
samples the initial address and increments an internal address counter after each
transfer. The incremented address is not pipelined on the bus. If the burst access is a
read from host to ADSP-21160N, ADSP-21160N automatically increments the address
as long as BRST is asserted. BRST is asserted after the initial access of a burst transfer.
It is asserted for every cycle after that, except for the last data request cycle (denoted by
RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s BRST pin
maintains the input at the level it was last driven (only enabled on the ADSP-21160N
with ID2–0 = 00x).
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to
an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access. The ADSP-21160N
deasserts ACK as an output to add wait states to a synchronous access of its internal
memory, by a synchronous host or another DSP in a multiprocessor configuration. ACK
has a 2 k
internal pull-up resistor that is enabled on the ADSP-21160N with
ID2–0 = 00x.
SBTS
I/S
Suspend Bus and Three-State. External devices can assert
SBTS (low) to place the
external bus address, data, selects, and strobes in a high impedance state for the following
cycle. If the ADSP-21160N attempts to access external memory while
SBTS is asserted,
the processor will halt and the memory access will not be completed until
SBTS is
deasserted.
SBTS should only be used to recover from host processor and/or ADSP-
21160N deadlock or used with a DRAM controller.
IRQ2–0
I/A
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be
either edge-triggered or level-sensitive.
FLAG3–0
I/O/A
Flag Pins. Each is configured via control bits as either an input or output. As an input,
it can be tested as a condition. As an output, it can be used to signal external peripherals.
TIMEXP
O
Timer Expired. Asserted for four Core Clock cycles when the timer is enabled and
TCOUNT decrements to zero.
HBR
I/A
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-
21160N’s external bus. When
HBR is asserted in a multiprocessing system, the ADSP-
21160N that is bus master will relinquish the bus and assert
HBG. To relinquish the
bus, the ADSP-21160N places the address, data, select, and strobe lines in a high
impedance state.
HBR has priority over all ADSP-21160N bus requests (BR6–1) in a
multiprocessing system.
HBG
I/O
Host Bus Grant. Acknowledges an
HBR bus request, indicating that the host processor
may take control of the external bus.
HBG is asserted (held low) by the ADSP-21160N
until
HBR is released. In a multiprocessing system, HBG is output by the ADSP-
21160N bus master and is monitored by all others. After
HBR is asserted, and before
HBG is given, HBG will float for 1 t
CLK (1 CLKIN cycle). To avoid erroneous grants,
HBG should be pulled up with a 20 k
to 50 k external resistor.
CS
I/A
Chip Select. Asserted by host processor to select the ADSP-21160N, for asynchronous
transfer protocol.
REDY
O (O/D)
Host Bus Acknowledge. The ADSP-21160N deasserts REDY (low) to add wait states
to an asynchronous host access when
CS and HBR inputs are asserted.
DMAR1
I/A
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA
services.
DMAR1 has a 20 k
internal pull-up resistor that is enabled on the ADSP-
21160N with ID2–0 = 00x.
Table 2. Pin Function Descriptions (continued)
Pin
Type
Function
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ADSP-21160NKB-95 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21160NKB-X 制造商:Analog Devices 功能描述:
ADSP-21160NKBZ-100 功能描述:IC DSP CONTROLLER 32BIT 400-BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21161N 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer
ADSP-21161NCCA-100 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
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