DMA Handshake See Table 18 and Figure 21. These specifications describe the three DMA handshake modes. In all three mod" />
參數(shù)資料
型號(hào)： ADSP-21160NKB-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/48頁(yè)
文件大小： 0K
描述： IC DSP CONTROLLER 32BIT 400BGA
產(chǎn)品培訓(xùn)模塊： SHARC Processor Overview
標(biāo)準(zhǔn)包裝： 1
系列： SHARC®
類型： 浮點(diǎn)
接口： 主機(jī)接口，連接端口，串行端口
時(shí)鐘速率： 100MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.90V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 400-BBGA
供應(yīng)商設(shè)備封裝： 400-PBGA（27x27）
包裝： 托盤
ADSP-21160N
–32–
REV. 0
DMA Handshake
See Table 18 and Figure 21. These specifications describe the
three DMA handshake modes. In all three modes,
DMARx is
used to initiate transfers. For handshake mode,
DMAGx controls
the latching or enabling of data externally. For external hand-
shake mode, the data transfer is controlled by the ADDR31–0,
RDx, WRx, PAGE, MS3–0, ACK, and DMAGx signals. For
Paced Master mode, the data transfer is controlled by
ADDR31–0,
RDx, WRx, MS3–0, and ACK (not DMAG). For
Paced Master mode, the Memory Read-Bus Master, Memory
Write-Bus Master, and Synchronous Read/Write-Bus Master
timing specifications for ADDR31–0,
RDx, WRx, MS3–0,
PAGE, DATA63–0, and ACK also apply.
Table 18. DMA Handshake
Parameter
Min
Max
Unit
Timing Requirements
tSDRC
DMARx Setup Before CLKIN1
3ns
tWDR
DMARx Width Low (Nonsynchronous)2
0.5tCCLK+2.5
ns
tSDATDGL
Data Setup After
DMAGx Low3
tCK –0.5tCCLK –7
ns
tHDATIDG
Data Hold After
DMAGx High
2
ns
tDATDRH
Data Valid After
DMARx High3
tCK+3
ns
tDMARLL
DMARx Low Edge to Low Edge4
tCK
ns
tDMARH
DMARx Width High2
0.5tCCLK+1
ns
Switching Characteristics
tDDGL
DMAGx Low Delay After CLKIN
0.25tCCLK+1
0.25tCCLK+9
ns
tWDGH
DMAGx High Width
0.5tCCLK –1 +HI
ns
tWDGL
DMAGx Low Width
tCK –0.5tCCLK –1
ns
tHDGC
DMAGx High Delay After CLKIN
tCK – 0.25tCCLK+1.5
tCK – 0.25tCCLK+9
ns
tVDATDGH
Data Valid Before
DMAGx High5
tCK – 0.25tCCLK –8
tCK – 0.25tCCLK+5
ns
tDATRDGH
Data Disable After
DMAGx High6
0.25tCCLK – 3
0.25tCCLK+1.5
ns
tDGWRL
WRx Low Before DMAGx Low
–1.5
2
ns
tDGWRH
DMAGx Low Before WRx High
tCK –0.5tCCLK –2+ W
ns
tDGWRR
WRx High Before DMAGx High7
–1.5
2
ns
tDGRDL
RDx Low Before DMAGx Low
–1.5
2
ns
tDRDGH
RDx Low Before DMAGx High
tCK –0.5tCCLK–2+W
ns
tDGRDR
RDx High Before DMAGx High7
–1.5
2
ns
tDGWR
DMAGx High to WRx, RDx, DMAGx
Low
0.5tCCLK –2 +HI
ns
tDADGH
Address/Select Valid to
DMAGx High
15.5
ns
tDDGHA
Address/Select Hold after
DMAGx High
1
ns
W = (number of wait states specified in WAIT register)
tCK.
HI = tCK (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1 Only required for recognition in the current cycle.
2 Maximum throughput using
DMARx/DMAGx handshaking equals tWDR + tDMARH = (0.5tCCLK+1) + (0.5tCCLK+1)=10.0 ns (100 MHz). This throughput
limit applies to non-synchronous access mode only.
3 tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of
the write, the data can be driven tDATDRH after DMARx is brought high.
4 Use tDMARLL if DMARx transitions synchronous with CLKIN. Otherwise, use tWDR and tDMARH.
5 tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then
tVDATDGH =tCK –.25tCCLK –8+ (n × tCK) where n equals the number of extra cycles that the access is prolonged.
6 See Example System Hold Time Calculation on Page 41 for calculation of hold times given capacitive and dc loads.
7 This parameter applies for synchronous access mode only.
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