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| 型號： | ADSP-2104BPZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 68PLCC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 19 |
| 系列： | ADSP-21xx |
| 類型： | 定點(diǎn) |
| 接口： | 同步串行端口（SSP） |
| 時鐘速率： | 20MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 1.5kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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ADSP-2104/ADSP-2109
REV. 0
–5–
The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
The interrupt force and clear register, IFC, is a write-only register
that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the ASTAT, MSTAT, and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the
interrupt instruction is executed.
Pin Definitions
Table II shows pin definitions for the ADSP-2104/ADSP-2109
processors. Any inputs not used must be tied to VDD.
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-2104/ADSP-2109,
with two serial I/O devices, a boot EPROM, and optional external
program and data memory. A total of 14.25K words of data
memory and 14.5K words of program memory is addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-2104/ADSP-2109 also provides either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT0).
Clock Signals
The ADSP-2104/ADSP-2109’s CLKIN input may be driven by
a crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the processor includes an on-chip oscillator circuit, an
external crystal may also be used. The crystal should be con-
nected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 2. A parallel-resonant, fundamen-
tal frequency, microprocessor-grade crystal should be used.
Table II. ADSP-2104/ADSP-2109 Pin Definitions
Pin
# of
Input /
Name(s)
Pins
Output
Function
Address
14
O
Address outputs for program, data and boot memory.
Data1
24
I/O
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
RESET
1
I
Processor Reset Input
IRQ2
1
I
External Interrupt Request #2
BR
2
1
I
External Bus Request Input
BG
1
O
External Bus Grant Output
PMS
1
O
External Program Memory Select
DMS
1
O
External Data Memory Select
BMS
1
O
Boot Memory Select
RD
1
O
External Memory Read Enable
WR
1
O
External Memory Write Enable
MMAP
1
I
Memory Map Select Input
CLKIN, XTAL
2
I
External Clock or Quartz Crystal Input
CLKOUT
1
O
Processor Clock Output
VDD
Power Supply Pins
GND
Ground Pins
SPORT0
5
I/O
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
SPORT1
5
I/O
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
or Interrupts & Flags:
IRQ0
(RFS1)
1
I
External Interrupt Request #0
IRQ1
(TFS1)
1
I
External Interrupt Request #1
FI (DR1)
1
I
Flag Input Pin
FO (DT1)
1
O
Flag Output Pin
NOTES
1Unused data bus lines may be left floating.
2BR must be tied high (to V
DD) if not used.
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