Timing Requirement: t
參數(shù)資料
型號(hào): ADSP-2104BPZ-80
廠商: Analog Devices Inc
文件頁數(shù): 16/36頁
文件大?。?/td> 0K
描述: IC DSP CONTROLLER 16BIT 68PLCC
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 19
系列: ADSP-21xx
類型: 定點(diǎn)
接口: 同步串行端口(SSP)
時(shí)鐘速率: 20MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.5kB
電壓 - 輸入/輸出: 5.00V
電壓 - 核心: 5.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(24.23x24.23)
包裝: 管件
ADSP-2104/ADSP-2109
REV. 0
–23–
Frequency
20 MHz
Dependency
Parameter
Min
Max
Min
Max
Unit
Timing Requirement:
tBH
BR Hold after CLKOUT High
1
17.5
0.25tCK + 5
ns
tBS
BR Setup before CLKOUT Low
1
32.5
0.25tCK + 20
ns
Switching Characteristic:
tSD
CLKOUT High to DMS,
32.5
0.25tCK + 20
ns
PMS, BMS, RD, WR Disable
tSDB
DMS, PMS, BMS, RD, WR
0
ns
Disable to BG Low
tSE
BG High to DMS, PMS,
0
ns
BMS, RD, WR Enable
tSEC
DMS, PMS, BMS, RD, WR
2.5
0.25tCK – 10
ns
Enable to CLKOUT High
NOTES
1If BR meets the t
BS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulse width greater than 10 ns.
Note: BG is asserted in the cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
BUS REQUEST/GRANT
CLKOUT
PMS, DMS
BMS, RD
WR
BR
BG
CLKOUT
tSD
tSDB
tSE
tSEC
tBH
tBS
Figure 21. Bus Request/Grant
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