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參數(shù)資料
| 型號： | ADSP-2104BPZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 68PLCC |
| 產品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 19 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 同步串行端口（SSP） |
| 時鐘速率： | 20MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 1.5kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
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ADSP-2104/ADSP-2109
–4–
REV. 0
The ADSP-2104/ADSP-2109 can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a master
RESET
signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, the ADSP-2104 to use a 150 ns EPROM as external
boot memory. Multiple programs can be selected and loaded
from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2104/ADSP-2109 processor includes two synchro-
nous serial ports (“SPORTs”) for serial communications and
multiprocessor communication.
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
Function
SCLK
Serial Clock (I/O)
RFS
Receive Frame Synchronization (I/O)
TFS
Transmit Frame Synchronization (I/O)
DR
Serial Data Receive
DT
Serial Data Transmit
The serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
Flexible Framing—The SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.
Different Word Lengths—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Companding in Hardware—Each SPORT provides optional
A-law and
-law companding according to CCITT recommen-
dation G.711.
Flexible Interrupt Scheme—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability (SPORT0 Only)—SPORT0
provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T1 or CEPT
interfaces, or as a network communication scheme for multiple
processors.
Alternate Configuration—SPORT1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
Interrupts
The interrupt controller lets the processor respond to interrupts
with a minimum of overhead. Up to three external interrupt
input pins, IRQ0, IRQ1, and IRQ2, are provided. IRQ2 is
always available as a dedicated pin; IRQ1 and IRQ0 may be
alternately configured as part of Serial Port 1. The ADSP-2104/
ADSP-2109 also supports internal interrupts from the timer,
and serial ports. The interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities are shown in Table I.
Table I. Interrupt Vector Addresses & Priority
ADSP-2104/ADSP-2109
Interrupt
Source
Vector Address
RESET
Startup
0x0000
IRQ2
0x0004 (High Priority)
SPORT0 Transmit
0x0008
SPORT0 Receive
0x000C
SPORT1 Transmit or IRQ1
0x0010
SPORT1 Receive or IRQ0
0x0014
Timer
0x0018 (Low Priority)
The ADSP-2104/ADSP-2109 uses a vectored interrupt scheme:
when an interrupt is acknowledged, the processor shifts program
control to the interrupt vector address corresponding to the
interrupt received. Interrupts can be optionally nested so that a
higher priority interrupt can preempt the currently executing
interrupt service routine. Each interrupt vector location is four
instructions in length so that simple service routines can be
coded entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
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