參數(shù)資料
型號(hào)： ADS62P42IRGCRG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 77/78頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SER/PAR 65M 64VQFN
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)差分，單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
TIMING CHARACTERISTICS
– LVDS AND CMOS MODES
(1)
Typical values are specified at 25
°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock,
1.5 VPP clock amplitude, CL = 5 pF
(2), I
O = 3.5 mA, RL = 100
(3), no internal termination, unless otherwise noted.
Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V,
unless otherwise specified.
ADS62P45
ADS62P44
ADS62P43
ADS62P42
FS = 125 MSPS
FS = 105 MSPS
FS = 80 MSPS
FS = 65 MSPS
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Aperture
ta
0.7
1.5
2.5
0.7
1.5
2.5
0.7
1.5
2.5
0.7
1.5
2.5
ns
delay
| ta1 - ta2 | ,
Channel-to-channel
50
within the same
Aperture
device
delay
ps
| ta1 - ta2 | ,
matching
Channel-to-channel
450
across two devices at
same temperature
Aperture
tj
150
fs rms
jitter
from global power
15
50
15
50
15
50
15
50
μs
down
Wake-up
time
from standby
15
50
15
50
15
50
15
50
μs
(to valid
from output
CMOS
100
200
100
200
100
200
100
200
ns
data)
buffer
LVDS
200
500
200
500
200
500
200
500
ns
disable
default, after reset
14
clock cycles
with low latency mode
10
clock cycles
Latency
enabled
with decimation filter
15
clock cycles
enabled
DDR LVDS MODE(4), DRVDD = 3.0 V to 3.6 V
Data valid (6) to
Data setup
tsu
zero-cross of
0.6
1.5
1.0
2.3
2.4
3.8
5.2
ns
time(5)
CLKOUTP
Zero-cross of
Data hold
th
CLKOUTP to data
1.0
2.3
1.0
2.3
1.0
2.3
1.0
2.3
ns
time(5)
becoming invalid(6)
Input clock rising edge
Clock
zero-cross to output
tPDI
propagation
3.5
5.5
7.5
3.5
5.5
7.5
3.5
5.5
7.5
3.5
5.5
7.5
ns
clock rising edge
delay
zero-cross
Duty cycle of
LVDS bit
differential clock,
clock duty
(CLKOUTP-
46% 50%
53%
46% 50%
53%
46%
50%
53% 46%
50%
53%
cycle
CLKOUTM)
10
≤ Fs ≤ 125 MSPS
Rise time measured
from
–50 mV to 50
Data rise
mV
tr
time
Fall time measured
70
100
170
70
100
170
70
100
170
70
100
170
ps
tf
Data fall
from 50 mV to
–50
time
mV
1
≤ Fs ≤ 125 MSPS
Rise time measured
from
–50 mV to 50
Output clock
mV
tCLKRISE
rise time
Fall time measured
70
100
170
70
100
170
70
100
170
70
100
170
ps
tCLKFALL
Output clock
from 50 mV to
–50
fall time
mV
1
≤ Fs ≤ 125 MSPS
(1)
Timing parameters are specified by design and characterization and not tested in production.
(2)
CL is the effective external single-ended load capacitance between each output pin and ground.
(3)
IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
(4)
Measurements are done with a transmission line of 100-
characteristic impedance between the device and the load.
(5)
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(6)
Data valid refers to logic high of +100 mV and logic low of
–100 mV.
8
Copyright
2007–2012, Texas Instruments Incorporated
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