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參數(shù)資料
| 型號： | ADS62P42IRGCRG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 60/78頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT SER/PAR 65M 64VQFN |
| 產品培訓模塊： | Data Converter Basics |
| 標準包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 65M |
| 數(shù)據接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-VQFN 裸露焊盤（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，單極 |
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y(n) +
1
211
[h0
x(n) ) h1
x(n * 1) ) h2
x(n * 2) ) AAA ) h11
x(n * 11) ) h11
x(n * 12) ) AAA ) h1
x(n * 22) ) h0
x(n * 23)]
y(n) +
1
211
x[h0
x(n) ) h1
x(n * 1) ) h2
x(n * 2) ) AAA ) h10
x(n * 10) ) h11
x(n * 11) ) h10
x(n * 12) ) AAA ) h1
x(n * 21) ) h0
x(n * 22)]
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
Decimation Filters
ADS62P4X includes option to decimate the ADC output data with in-built low pass, high pass or band pass
filters.
The decimation rate and type of filter can be selected using register bits ( DECIMATION RATE) and (
DECIMATION FILTER TYPE). Decimation rates of 2, 4, or 8 are available and either low pass, high pass or band
pass filters can be selected (see Table 24). By default, the decimation filter is disabled
– use register bit
<FILTER ENABLE> to enable it.
Table 24. Decimation Filter Modes
COMBINATION OF DECIMATION RATES AND FILTER TYPES
<DECIMATIO
<FILTER
<DECIMATION
N FILTER
COEFF
<FILTER
RATE
>
FREQ
SELECT
ENABLE
>
DECIMATION
TYPE OF FILTER
BAND
>
Decimate by 2
In-built low-pass filter (pass band = 0 to Fs/4)
0
1
In-built high-pass filter (pass band = Fs/4 to Fs/2)
0
1
0
1
Decimate by 4
In-built low-pass filter (pass band = 0 to Fs/8)
0
1
0
1
0
1
0
1
0
1
In-built 2nd band-pass filter (pass band = Fs/8 to Fs/4)
0
1
0
1
In-built 3rd band-pass filter (pass band = Fs/4 to 3Fs/8)
In-built last band-pass filter (pass band = 3Fs/8 to Fs/2)
0
1
0
1
Decimate by 2
Custom filter (user programmable coefficients)
0
X
1
Decimate by 4
Custom filter (user programmable coefficients)
0
1
X
1
Decimate by 8
Custom filter (user programmable coefficients)
1
0
X
1
No decimation
Custom filter (user programmable coefficients)
0
1
X
1
0
Decimation Filter Equation
The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit
signed). The filter equation is:
(3)
By setting the register bit
<ODD TAP ENABLE> = 1, a 23-tap FIR is implemented:
(4)
In the above equations,
h0, h1
…h(huán)11 are 12-bit signed representation of the coefficients,
x(n) is the input data sequence to the filter
y(n) is the filter output sequence
Pre-defined Coefficients
The in-built filter types (low pass, high pass, and band pass) use pre-defined coefficients. The frequency
response of the in-built filters is shown in Figure 102 and Figure 103.
Copyright
2007–2012, Texas Instruments Incorporated
63
Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADS62P42IRGCT | 功能描述:模數(shù)轉換器 - ADC Dual 14B 65MSPS ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS62P42IRGCTG4 | 功能描述:模數(shù)轉換器 - ADC DUAL 14B 65MSPS Para ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS62P42RGC | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs |
| ADS62P43 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS |
| ADS62P43EVM | 功能描述:數(shù)據轉換 IC 開發(fā)工具 ADS62P43 Eval Mod RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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