Table 7. Summary of" />
參數(shù)資料
型號: ADS62P42IRGCRG4
廠商: Texas Instruments
文件頁數(shù): 13/78頁
文件大小: 0K
描述: IC ADC 14BIT SER/PAR 65M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
SERIAL REGISTER MAP
Table 7. Summary of Functions Supported by Serial Interface (1)
REGISTER
REGISTER FUNCTIONS
ADDRESS
A7
–A0 IN
D7
D6
D5
D4
D3
D2
D1
D0
HEX
<RST>
<SERIAL
00
0
READOUT
Software
>
Reset
<CLKOUT
10
0
STRENGTH
>
<LVDS CURRENT>
<CURRENT DOUBLE>
11
0
<DATAOUT STRENGTH>
LVDS buffer current
LVDS buffer current double
programmability
<LVDS TERMINATION>
12
0
Internal termination programmability
13
0
<OFFSET FREEZE>
0
<OUTPUT
<POWER DOWN MODES>
<REF>
<OVRD>
INTERFACE
>
<COARSE GAIN>
14
0
and
Internal/External
Over-ride bit
LVDS or CMOS
3.5 dB gain
reference
MUX mode
interface
<DATA FORMAT>
Bit/Byte wise
16
0
<TEST PATTERNS>
2s complement or
(LVDS only)
straight binary
<FINE GAIN>
17
0
0 to 6 dB gain in 0.5 dB steps
18
<CUSTOM LOW> Lower 8 bits
19
0
<CUSTOM HIGH> Upper 6 bits
<OFFSET TC>
<GAIN CORRECTION>
<LOW
1A
LATENCY
>
Offset correction time constant
0 to 0.5 dB, steps of 0.05 dB
<OFFSET
<FILTER COEFF
EN
>
SELECT
>
<FILTER Enable>
<DECIMATION RATE>
<ODD TAP
1B
0
Offset
Enable
>
In-built or custom
Enable digital filtering
Decimate by 2, 4, 8
correction
coefficients
enable
<DECIMATION FILTER
1D
0
FREQ BANDS
>
1E to 2F
<FILTER COEFFICIENTS> 12 coefficients, each 12 bit signed
(1)
Multiple functions in a register can be programmed in a single write operation.
20
Copyright
2007–2012, Texas Instruments Incorporated
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