參數(shù)資料
型號: ADS62P42IRGCRG4
廠商: Texas Instruments
文件頁數(shù): 10/78頁
文件大小: 0K
描述: IC ADC 14BIT SER/PAR 65M 64VQFN
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)差分,單極
0
0
1
R EGIST ER A DDR ESS ( A7: A0) = 0x00
REGISTER DAT A ( D7:D 0) = 0x01
SDA TA
SC LK
SEN
A) Enable serial read back (<SERIAL READOUT> = 1)
(Serial register writes are disabled)
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDA TA
SC LK
SEN
SDOUT
B) Read contents of register 0x14.
This register has been initialized with 0xB0
(over-ride bit set, LVDS interface, 3.5dB coarse gain, internal reference, normal operation)
REGISTER ADD RESS (A 7:A 0) = 0x14
R EGIST ER D ATA (D 7:D 0) = XX ( do n’ t care)
SDOUT
1
0
1
0
Pin SD OU T is NOT in hig h- im ped ance stat e; it is f orced low o r h ig h b y th e de vice ( <SERIA L REA DOUT > = 0)
Pin SDOUT fu nc tio ns as serial reado u t ( <SERIA L REA DOUT > = 1)
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
Figure 7. Serial Readout
RESET TIMING
Typical values at 25
°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless otherwise
noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Delay from power-up of AVDD and DRVDD to RESET pulse
t1
Power-on delay
5
ms
active
t2
Reset pulse width
Pulse width of active RESET signal
10
ns
t3
Register write delay
Delay from RESET disable to SEN active
25
ns
tPO
Power-up time
Delay from power-up of AVDD and DRVDD to output stable
7
ms
18
Copyright
2007–2012, Texas Instruments Incorporated
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