參數(shù)資料
型號： ADS62P42IRGCRG4
廠商： Texas Instruments
文件頁數(shù)： 51/78頁
文件大?。?/td> 0K
描述： IC ADC 14BIT SER/PAR 65M 64VQFN
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標準包裝： 2,000
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個差分，單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
POWER DOWN
ADS62P4X has three powerdown modes
– power down global, individual channel standby and individual channel
output buffer disable. These can be set using either the serial register bits or using the control pins CTRL1 to
CTRL3.
Table 21. Powerdown Modes
CONFIGURE USING
WAKE-UP
POWERDOWN MODES
SERIAL INTERFACE
PARALLEL CONTROL PINS
TIME
<POWER DOWN MODES>
CTRL1
CTRL2
CTRL3
Normal operation
000
low
—
Channel A output buffer disabled
001
low
high
Fast (100 ns)
Channel B output buffer disabled
010
low
high
low
Fast (100 ns)
Channel A and B output buffer disabled
011
low
high
Fast (100 ns)
Global power down
100
high
low
Slow (15
μS)
Channel A standby
101
high
low
high
Fast (100 ns)
Channel B standby
110
high
low
Fast (100 ns)
Multiplexed (MUX) mode
– Output data of
channel A and B is multiplexed and available
111
high
—
on DB13 to DB0 pins.
Power Down Global
In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are
powered down resulting in reduced total power dissipation of about 50 mW. The output buffers are in high
impedance state. The wake-up time from the global power down to data becoming valid in normal mode is
typically 15
μs.
Channel Standby (Individual or Both Channels)
This mode allows the individual ADCs to be powered down. The internal references are active and this results in
fast wake-up time, about 100 ns. The total power dissipation in standby is about 482 mW.
Output Buffer Disable (Individual or Both Channels)
Each channel
’s output buffer can be disabled and put in high impedance state -- wakeup time from this mode is
fast, about 100 ns.
Input Clock Stop
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1
MSPS. The power dissipation is about 140 mW.
POWER SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated in the device. Externally, they can be driven from separate supplies or derived from a single supply.
Copyright
2007–2012, Texas Instruments Incorporated
55
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ADS62P42RGC 制造商:TI 制造商全稱:Texas Instruments 功能描述:Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs
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