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參數(shù)資料
| 型號： | ADS1194CZXGT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封裝： | 8 X 8 MM, GREEN, PLASTIC, NFBGA-64 |
| 文件頁數(shù)： | 25/76頁 |
| 文件大小： | 1193K |
| 代理商： | ADS1194CZXGT |
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START
Opcode
(1)
S
RTPin
TA
DIN
t
DR
t
SETTLE
DRDY
STOP
Opcode
(1)
or
t
SDSU
t
DSHD
STOPOpcode
DRDY andDOUT
STARTPin
or
STOP(1)
SBAS471B
– APRIL 2010 – REVISED APRIL 2011
Continuous Mode
Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in
Figure 32, the DRDY output goes high when conversions are started and goes low when data are ready.
Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted.
When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to
complete. Figure 33 and Table 8 show the required timing of DRDY to the START pin and the START/STOP
opcode commands when controlling conversions in this mode. To keep the converter running continuously, the
START pin can be permanently tied high. Note that when switching from pulse mode to continuous mode, the
START signal is pulsed or a STOP command must be issued followed by a START command.
This conversion mode is ideal for applications that require a fixed continuous stream of conversion results.
(1)
START and STOP opcode commands take effect on the seventh SCLK falling edge.
Figure 32. Continuous Conversion Mode
(1)
START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.
Figure 33. START to DRDY Timing
Table 8. Timing Characteristics for Figure 33(1)
SYMBOL
DESCRIPTION
MIN
UNIT
START pin low or STOP opcode to DRDY setup time
tSDSU
16
1/fCLK
to halt further conversions
START pin low or STOP opcode to complete current
tDSHD
16
1/fCLK
conversion
(1)
START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission.
Copyright
2010–2011, Texas Instruments Incorporated
31
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