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參數(shù)資料
| 型號： | ADM1029ARQZ-R7 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 9/50頁 |
| 文件大?。?/td> | 402K |
| 描述： | IC SENSOR 2TEMP/FAN CTRL 24QSOP |
| 產(chǎn)品變化通告： | QSOP 24ld Pkg (MSL) Change 17/Jun/2010 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 功能： | 風(fēng)扇控制，溫度監(jiān)控器 |
| 傳感器類型： | 內(nèi)部和外部 |
| 感應(yīng)溫度： | 0°C ~ 100°C，外部傳感器 |
| 精確度： | ±1°C 本地，±3°C 遠(yuǎn)程 |
| 拓?fù)洌?/td> | ADC，風(fēng)扇控制，寄存器庫 |
| 輸出類型： | 開路漏極 |
| 輸出警報： | 是 |
| 輸出風(fēng)扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-QSOP |
| 包裝： | 帶卷 (TR) |
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ADM1029
http://onsemi.com
9
write to the slave device. If the R/W
bit is a 1 the
master will read from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
acknowledge bit from the slave device. Transitions
on the data line must occur during the low period
of the clock signal and remain stable during the
high period, as a low-to-high transition when the
clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted
over the serial bus in a single READ or WRITE
operation is limited only by what the master and
slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In WRITE mode,
the master will pull the data line high during the
tenth clock pulse to assert a STOP condition. In
READ mode, the master device will override the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
will then take the data line low during the low
period before the tenth clock pulse, high during the
tenth clock pulse to assert a STOP condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation, because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
Figure 18. Writing a Register Address to the Address Pointer Register,
then Writing Data to the Selected Register
R/W
0
SCL
SDA
1
0
1
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1029
START BY
MASTER
1
9
1
ACK. BY
ADM1029
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1029
STOP BY
MASTER
1
9
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
Figure 19. Writing to the Address Pointer Register Only
0
SCL
SDA
1
0
1
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADM1029
START BY
MASTER
1
9
1
ACK. BY
ADM1029
9
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
R/W
Figure 20. Reading Data from a Previously Selected Register
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK.
BY MASTER
START BY
MASTER
9
1
ACK. BY
ADM1029
9
STOP BY
MASTER
0
1
0
1
A2
A1
A0
1
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADM1029
R/W
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