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參數(shù)資料
| 型號： | ADM1029ARQZ-R7 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 17/50頁 |
| 文件大?。?/td> | 402K |
| 描述： | IC SENSOR 2TEMP/FAN CTRL 24QSOP |
| 產(chǎn)品變化通告： | QSOP 24ld Pkg (MSL) Change 17/Jun/2010 |
| 標(biāo)準包裝： | 1,000 |
| 功能： | 風(fēng)扇控制，溫度監(jiān)控器 |
| 傳感器類型： | 內(nèi)部和外部 |
| 感應(yīng)溫度： | 0°C ~ 100°C，外部傳感器 |
| 精確度： | ±1°C 本地，±3°C 遠程 |
| 拓撲： | ADC，風(fēng)扇控制，寄存器庫 |
| 輸出類型： | 開路漏極 |
| 輸出警報： | 是 |
| 輸出風(fēng)扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-QSOP |
| 包裝： | 帶卷 (TR) |
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ADM1029
http://onsemi.com
17
an analog input crosses the corresponding AIN low
limit, the direction depending on the setting of Bit 3 of
the AIN control register. (0 = alarm when input goes
below low limit, 1 = alarm when input goes above low
limit).
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If a thermal override occurs while the ADM1029 is in
sleep mode, all fans controlled by the ADM1029 will
run at alarm speed.
Hot-plug Speed
Hot-plug speed is set by the four LSBs of the Fan 1 and
Fan 2 Configuration Registers (addresses 68h and 69h). The
PWM frequency is set by Bits 4 and 5 of these registers,
while Bits 6 and 7 set the number of pulses per revolution for
fan speed measurement.
Fan(s) will run at hot-plug speed if any of the following
conditions occur, assuming the condition has not been
masked using the Fan Event Mask Registers:
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If a fan is unplugged, the other fan (if any) controlled
by the ADM1029 will run at hot-plug speed.
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Setting Bit 0 of register 08h forces Fan 1 to run at
hot-plug speed (Set Fan x Hot-plug Speed).
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> Setting Bit 1 of register 08h forces Fan 2 to run at
hot-plug speed (Set Fan x Hot-plug Speed).
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> When a GPIO pin is configured as an input by setting
Bit 0 of the corresponding GPIO Behavior Register,
and Bit 5 of the GPIO Behavior Register is also set, all
fans controlled by the ADM1029 will go to hot-plug
speed when the logic input is asserted (high or low,
depending on the polarity bit, Bit 1 of the
corresponding GPIO Behavior Register).
?SPAN class="pst ADM1029ARQZ-R7_2295375_3"> If Bit 6 of a Fan Fault Action Register is set (18h for
Fan 1, 19h for Fan 2) the corresponding fan will go to
hot-plug speed when CFAULT
is pulled low by an
external source.
NOTE: if operating conditions and register settings are such that
both alarm speed and hot-plug speed would be triggered,
which one takes priority is determined by Bit 5 of the Fan 1
and Fan 2 Status Registers (addresses 10h and 11h). If this
bit is set, hot-plug speed takes priority. If it is cleared, alarm
speed takes priority.
Full Speed
Fans will run at full speed if the corresponding bits in the
Set Fan x Full Speed Register (address 09h) are set: Bit 0 for
Fan 1 and Bit 1 for Fan 2.
Fan Mask Registers
The effect of various conditions on fan speed can be
enabled or disabled by mask registers. In all these registers,
setting Bit 0 of the register enables Fan 1 to go to alarm
speed or hot-plug speed if the corresponding event occurs,
while setting Bit 1 enables Fan 2. Clearing these bits masks
the effect of the corresponding event on fan speed.
Registers 20h and 21h are Fan Event Mask Registers.
Bits 0 and 1 of register 20h enable (bit set) or mask (bit clear)
the effect of a Fan 1 fault (underspeed or fault input) on
Fan 1 and Fan 2 speed. Similarly, Bits 0 and 1 of register 21h
enable (bit set) or mask (bit clear) the effect of a Fan 2 Fault
on Fan 1 and Fan 2 speed.
Registers 38h to 3Eh are GPIO X Event Mask Registers.
Bits 0 and 1 of these registers enable or mask the effect of a
GPIO assertion on Fan 1 and Fan 2 speed.
NOTE: Registers 48h to 4Ah are Temp. Cooling Action Registers.
Bits 0 and 1 of these registers enable or mask the effect of
Local, Remote 1, and Remote 2 temperature faults on
Fan 1 and Fan 2 speed. These registers also determine
which temperature channel controls each fan in automatic
fan speed control mode, as described later.
Registers 58h and 59h are AIN Event Mask Registers.
Bits 0 and 1 of these registers enable or mask the effect of an
AIN out-of-limit event on Fan 1 and Fan 2 speed.
Modes of Operation
The ADM1029 has three different modes of operation.
These modes determine the behavior of the system.
1. PWM Duty Cycle Select Mode (directly sets fan speed
under software control)
2. Thermal Trip Mode
3. Automatic Fan Speed Control Mode
PWM Duty Cycle Select Mode
The ADM1029 may be operated under software control
by clearing bits <1:0> of the three Temp Cooling Action
Registers (Reg 0x48, 0x49, 0x4A). Once under Software
Control, each fan speed may be controlled by programming
values of PWM Duty Cycle in to the device. Values of PWM
Duty Cycle between 0% to 100% may be written to the four
LSBs of the Fan 1 and Fan 2 Minimum/Alarm Speed
Registers (addresses 60h, 61h). to control the speed of each
fan. Table 9 shows the relationship between hex values
written to the Minimum/Alarm Speed Registers and PWM
duty cycle obtained.
Table 9. PWM DUTY CYCLE SELECT MODE
Hex Value
PWM Duty Cycle
00
0%
01
7%
02
14%
03
20%
04
27%
05
33% Recommended
06
40%
07
47%
08
53%
09
60%
0A
67%
0B
73%
0C
80%
0D
87%
0E
93%
0F
100% (Default)
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