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| 型號： | ADM1024EVB |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 15/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADM1024 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 其它名稱： | EVAL-ADM1024EB EVAL-ADM1024EB-ND |
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ADM1024
http://onsemi.com
22
can only be cleared by setting Bit 0 of Configuration
Register 2.
THERM will be cleared automatically if the temperature
falls at least 5 degrees below the limit for three consecutive
measurements.
ACPI Mode
In ACPI mode, THERM responds only to the hardware
temperature limits at addresses 13h, 14h, 17h, and 18h, not
to the software-programmed limits.
Figure 35. THERM Output in ACPI Mode
TEMP
HARDWARE
TRIP POINT
THERM
ANALOG
OUTPUT
PROGRAMMED
VALUE
55
0xFF
THERM
EXT
INPUT
THERM will go low if either the internal or external
hardware temperature limit is exceeded for three
consecutive measurements. It will remain low until the
temperature falls at least 5 degrees below the limit for three
consecutive measurements. While THERM is low, the
analog output will go to FFh to boost a controlled fan to full
speed.
RESET Input/Output
RESET (Pin 12) is an I/O pin that can function as an
open-drain output, providing a low going 20 ms output pulse
when Bit 4 of the Configuration Register is set to 1, provided
the reset function has first been enabled by setting Bit 7 of
Interrupt Mask Registers 2 to 1. The bit is automatically
cleared when the reset pulse is output. Pin 11 can also function
as a RESET input by pulling this pin low to reset the internal
registers of the ADM1024 to default values. Only those
registers that have power-on default values as listed in
Table 10 are affected by this function. The DAC, Value, and
Limit Registers are not affected.
NAND Tree Tests
A NAND gate is provided in the ADM1024 for
Automated Test Equipment (ATE) board level connectivity
testing. The device is placed into NAND Test Mode by
powering up with Pin 11 held high. This pin is automatically
sampled after powerup; if it is connected high, then the
NAND test mode is invoked.
In NAND test mode, all digital inputs may be tested as
illustrated below. NTEST_OUT/ADD will become the
NAND test output pin. To perform a NAND tree test, all pins
included in the NAND tree should first be driven high. Each
pin can then be toggled and a resulting toggle can be
observed on NTEST_OUT/ADD.
Allow for a typical propagation delay of 500 ns. The
structure of the NAND tree is shown in Figure 36.
Figure 36. NAND Tree
LATCH
C
Q
D
ENABLE
SDA
SCL
VID4
POWERON
RESET
NTEST_IN/AOUT
NTEST_OUT/ADD
VID0
VID1
VID2
VID3
FAN1
FAN2
Note that NTEST_OUT/ADD is a dual function line and
if both functions are required, then this line should not be
hardwired directly to VCC/GND. Instead it should be
connected via a 5 k
W resistor.
Note: If any of the inputs shown in Figure 36 are unused,
they should not be connected directly to ground, but via a
resistor such as 10 k
W. This will allow the Automatic Test
Equipment (ATE) to drive every input high so that the NAND
tree test can be carried out properly.
Using the ADM1024
Power-on Reset
When power is first applied, the ADM1024 performs a
power-on reset on several of its registers. Registers whose
power-on values are not shown have power-on conditions
that are indeterminate (this includes the Value and Limit
Registers). The ADC is inactive. In most applications, usually
the first action after power-on would be to write limits into the
Limit Registers. Power-on reset clears or initializes the
following registers (the initialized values are shown in
Table 12):
Configuration Registers 1 and 2
Channel Mode Register
Interrupt (INT) Status Registers 1 and 2
Interrupt (INT) Status Mirror Registers 1 and 2
Interrupt (INT) Mask Registers 1 and 2
VID/Fan Divisor Register
VID4 Register
Chassis Intrusion Clear Register
Test Register
Analog Output Register
Hardware Trip Registers
Initialization
Configuration Register initialization performs a similar,
but not identical, function to power-on reset. The Test
Register and Analog Output Register are not initialized.
Configuration Register initialization is accomplished by
setting Bit 7 of the Configuration Register high. This bit
automatically clears after being set.
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