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參數(shù)資料
| 型號： | ADM1024EVB |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 11/30頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADM1024 |
| 標準包裝： | 1 |
| 其它名稱： | EVAL-ADM1024EB EVAL-ADM1024EB-ND |
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ADM1024
http://onsemi.com
19
Mechatronics Inc.
P.O. Box 613
Preston, WA 98050
8004534569
Models—Various sizes available with tachometer output option.
Sanyo Denki, America, Inc.
468 Amapola Avenue
Torrance, CA 90501
3107835400
Models—109P Series
Chassis Intrusion Input
The chassis intrusion input is an active high
input/open-drain output intended for detection and
signalling of unauthorized tampering with the system. An
external circuit powered from the system’s CMOS backup
battery is used to detect and latch a chassis intrusion event,
whether or not the system is powered up. Once a chassis
intrusion has been detected and latched, the CI input will
generate an interrupt when the system is powered up.
The actual detection of chassis intrusion is performed by
an external circuit that will, for example, detect when the
cover has been removed. A wide variety of techniques may
be used for the detection, for example:
Microswitch that Opens or Closes when the Cover is
Removed
Reed Switch Operated by Magnet Fixed to the Cover
Hall-effect Switch Operated by Magnet Fixed to the
Cover
Phototransistor that Detects Light when the Cover is
Removed
The chassis intrusion interrupt will remain asserted until
the external detection circuit is reset. This can be achieved
by setting Bit 7 of the Chassis Intrusion Clear Register to
one, which will cause the CI pin to be pulled low for at least
20 ms. This register bit is self-clearing.
Figure 30. Chassis Intrusion Detector and Latch
74HC132
CI
MRD901
1N914
5.0 V
1N914
N1
N2
N3
N4
CMOS
BACKUP
BATTERY
1
2
3
4
5
6
7
14
13
12
11
10
9
8
470kW
100kW
10kW
The chassis intrusion circuit should be designed so that it
can be reset by pulling its output low. A suitable chassis
intrusion circuit using a photo-transistor is shown in
Figure 30. Light falling on the photo-transistor when the PC
cover is removed will cause it to turn on and pull up the input
of 1, thus setting the latch N3/N4. After the cover is
replaced, a low reset on the CI output will pull down the
input of N4, resetting the latch.
The chassis intrusion input can also be used for other types
of alarm input. Figure 31 shows a temperature alarm circuit
using an AD22105 temperature switch sensor. This produces
a low going output when the preset temperature is exceeded,
so the output is inverted by Q1 to make it compatible with the
CI input. Q1 can be almost any small-signal NPN transistor,
or a TTL or CMOS inverter gate may be used if one is
available. See the AD22105 data sheet for information on
selecting RSET.
Figure 31. Using the CI Input with a Temperature Sensor
CI
Q1
AD22105
TEMPERATURE
SENSOR
RSET
VCC
6
3
2
1
7
R1
10k
Note: The chassis intrusion input does not have a
protective clamp diode to VCC, as this could pull down the
chassis intrusion latch and reset it when the ADM1024 is
powered down.
The ADM1024 Interrupt Structure
The Interrupt Structure of the ADM1024 is shown in
Figure 32. As each measurement value is obtained and
stored in the appropriate value register, the value and the
limits from the corresponding limit registers are fed to the
high and low limit comparators. The result of each
comparison (1 = out of limit, 0 = in limit) is routed to the
corresponding bit input of the Interrupt Status Registers via
a data demultiplexer and used to set that bit high or low as
appropriate.
The Interrupt Mask Registers have bits corresponding to
each of the Interrupt Status Register Bits. Setting an
Interrupt Mask Bit high forces the corresponding Status Bit
output low, while setting an Interrupt Mask Bit low allows
the corresponding Status Bit to be asserted. After masking,
the status bits are all OR’d together to produce the INT
output, which will pull low if any unmasked status bit goes
high, i.e., when any measured value goes out of limit. The
ADM1024 also has a dedicated output for temperature
interrupts only, the THERM input/output Pin 2. The
function of this is described later.
The INT output is enabled when Bit 1 of Configuration
Register 1 (INT_Enable) is high, and Bit 3 (INT_Clear) is low.
The INT pin has an internal, 100 k
W pullup resistor.
VID/IRQ Inputs
The processor voltage ID inputs VID0 to VID4 can be
reconfigured as interrupt inputs by setting Bit 7 of the
Channel Mode Register (address 16h). In this mode they
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