- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10940 > ADAU1381BCPZ-RL (Analog Devices Inc)IC AUDIO CODEC STEREO LN 32LFCSP PDF資料下載
參數(shù)資料
| 型號： | ADAU1381BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CODEC STEREO LN 32LFCSP |
| 標(biāo)準包裝： | 5,000 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 無 |
| S/N 比，標(biāo)準 ADC / DAC (db)： | 97 / 100 |
| 動態(tài)范圍，標(biāo)準 ADC / DAC (db)： | 96.5 / 100 |
| 電壓 - 電源，模擬： | 1.8 V ~ 3.65 V |
| 電壓 - 電源，數(shù)字： | 1.63 V ~ 3.65 V |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
ADAU1381
Rev. B | Page 16 of 84
Table 10. Pin Function Descriptions
Pin No.
LFCSP
WLCSP
Mnemonic
Type1
Description
1
A6
CM
A_OUT
VDD/2 V Common-Mode Reference. A 10 μF to 47 μF decoupling capacitor should be
connected between this pin and ground to reduce crosstalk between the ADCs and
DACs. The material of the capacitors is not critical. This pin can be used to bias external
analog circuits, as long as they are not drawing current from CM (for example, the
noninverting input of an op amp).
2
C5
PDN
A_IN
Power-Down. Connecting this pin to GND powers down the chip. Resides in AVDD1
domain.
3
B6
AGND1
PWR
Analog Ground.
4
C6
AVDD1
PWR
Analog Power Supply. Should be equivalent to AVDD2.
5
D6
DVDDOUT
PWR
Digital Core Supply Decoupling Point. The digital supply is generated from an on-
board regulator and does not require an external supply. DVDDOUT should be
decoupled to DGND with a 100 nF capacitor.
6
E6
DGND
PWR
Digital Ground.
7
D5
GPIO
D_IO
Dedicated General-Purpose Input/Output.
8
C4
SCL/CCLK
D_IN
I2C Clock/SPI Clock.
9
E5
SDA/COUT
D_IO
I2C Data/SPI Data Output.
10
C3
ADDR0/CDATA
D_IN
I2C Address 0/SPI Data Input.
11
D4
ADDR1/CLATCH
D_IN
I2C Address 1/SPI Latch Signal.
12
E4
IOVDD
PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from
IOVDD, which sets the highest allowed input voltage for the digital input pins. The
current draw of this pin is variable because it is dependent on the loads of the digital
outputs. IOVDD should be decoupled to DGND with a 100 nF capacitor.
13
E3
DAC_SDATA/GPIO0
D_IO
DAC Serial Input Data/General-Purpose Input and Output.
14
D3
ADC_SDATA/GPIO1
D_IO
ADC Serial Output Data/General-Purpose Input and Output.
15
E2
BCLK/GPIO2
D_IO
Serial Data Port Bit Clock/General-Purpose Input and Output.
16
C2
LRCLK/GPIO3
D_IO
Serial Data Port Frame Clock/General-Purpose Input and Output.
17
E1
MCKI
D_IN
Master Clock Input.
18
D2
MCKO
D_OUT
Master Clock Output.
19
D1
AVDD2
PWR
Analog Power Supply. Should be equivalent to AVDD1.
20
C1
SPN
A_OUT
Speaker Amplifier Negative Signal Output.
21
N/A
NC
No Connect.
22
B1
SPP
A_OUT
Speaker Amplifier Positive Signal Output.
23
A1
AGND2
PWR
Speaker Amplifier Ground.
24
N/A
NC
No Connect.
25
B2
AOUTR
A_OUT
Line Output Amplifier, Right Channel.
26
A2
AOUTL
A_OUT
Line Output Amplifier, Left Channel.
27
B3
RMIC/RMICN/MICD2
A_IN
Right Channel Input from Single-Ended Source/Right Channel Input from Negative
Pseudo Differential Source/Digital Microphone Input 2.
28
A3
RMICP
A_IN
Right Channel Input from Positive Pseudo Differential Source.
29
B4
LMICP
A_IN
Left Channel Input from Positive Pseudo Differential Source.
30
A4
LMIC/LMICN/MICD1
A_IN
Left Channel Input from Single-Ended Source/Left Channel Input from Negative
Pseudo Differential Source/Digital Microphone Input 1.
31
B5
BEEP
A_IN
Beep Signal Input.
32
A5
MICBIAS
PWR
Microphone Bias.
THERM_PAD
(Exposed Pad)
Exposed Pad. The exposed pad is connected internally to the ADAU1381 grounds. For
increased reliability of the solder joints and maximum thermal capability, it is
recommended that the pad be soldered to the ground plane.
1 A_OUT = analog output, A_IN = analog input, PWR = power, D_IO = digital input/output, D_OUT = digital output, and D_IN = digital input.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-J3K-IX-S | CONVERTER MOD DC/DC 40V 75W |
| ADAU1361BCPZ-RL | IC CODEC 24B PLL 32LFCSP |
| VE-J3J-IX-S | CONVERTER MOD DC/DC 36V 75W |
| PK40N512VLQ100 | IC ARM CORTEX MCU 512K 144-LQFP |
| CS4245-DQZR | IC CODEC AUD STER 104DB 48-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1381BCPZ-RL7 | 功能描述:IC AUDIO CODEC STEREO LN 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| ADAU1382BCPZ | 制造商:Analog Devices 功能描述:STEREO AUDIO CODEC FOR DIG STILL CAM - Trays 制造商:Analog Devices 功能描述:IC AUDIO CODEC 24BIT 96KHZ LFCSP-32 制造商:Analog Devices 功能描述:IC, AUDIO CODEC, 24BIT, 96KHZ, LFCSP-32, Audio CODEC Type:Stereo, No. of ADCs:2, 制造商:Analog Devices 功能描述:AUDIO CODEC |
| ADAU1382BCPZ-R7 | 制造商:Analog Devices 功能描述:STEREO AUDIO CODEC FOR DIG STILL CAM - Tape and Reel 制造商:Analog Devices 功能描述:AUDIO CODEC |
| ADAU1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
| ADAU1401A | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。